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IDT70V3389S Datasheet(PDF) 13 Page - Integrated Device Technology

Part No. IDT70V3389S
Description  HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT70V3389S Datasheet(HTML) 13 Page - Integrated Device Technology

 
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6.42
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
13
ADDRESS
An
CLK
DATAOUT
Qx - 1
(2)
Qx
Qn
Qn + 2
(2)
Qn + 3
ADS
CNTEN
tCYC2
tCH2
tCL2
4832 drw 11
tSA
tHA
tSAD tHAD
tCD2
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
tSAD tHAD
tSCN tHCN
READ
WITH
COUNTER
Qn + 1
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
DATAIN
Dn + 3
Dn + 2
CE0
CLK
4832 drw 10
DATAOUT
Qn
Qn + 4
CE1
UB, LB
OE
tCH2
tCL2
tCYC2
tCKLZ
tCD2
tOHZ
tCD2
tSD
tHD
READ
WRITE
READ
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
(3)
(1)
tSW tHW
(4)
T im ing Wa ve for m of Pipe line d Re a d w it h Addre ss Count e r Adva nc e (1)
NOTES:
1. CE0, OE, UB, LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
T im ing Wa ve for m of Pipe line d Re a d-t o-Writ e -t o-Re a d ( OE Cont rolle d)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.


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