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IDT70V3389S Datasheet(PDF) 12 Page - Integrated Device Technology

Part No. IDT70V3389S
Description  HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT70V3389S Datasheet(HTML) 12 Page - Integrated Device Technology

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6.42
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
12
CLKL
R/WL
ADDRESSL
DATAINL
CLKR
R/WR
ADDRESSR
DATAOUTR
tSW
tHW
tSA
tHA
tSD
tHD
tSW
tHW
tSA
tHA
tCO(3)
tCD2
NO
MATCH
VALID
NO
MATCH
MATCH
MATCH
VALID
4832 drw 08
tDC
R/W
ADDRESS
An
An +1
An + 2
An + 2
An + 3
An + 4
DATAIN
Dn + 2
CE0
CLK
4832 drw 09
Qn
Qn + 3
DATAOUT
CE1
UB, LB
tCD2
tCKHZ
tCKLZ
tCD2
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
tCH2
tCL2
tCYC2
READ
NOP
READ
tSD tHD
(3)
(1)
tSW tHW
WRITE
(4)
T im ing Wa ve for m of Le ft Por t Writ e t o Pipe line d Right Por t Re a d(1,2)
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
be tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
port will be tCO + tCYC + tCD2).
T im ing Wa ve for m of Pipe line d Re a d-t o-Writ e -t o-Re a d (OE = V IL)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.


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