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IDT70V3389S Datasheet(PDF) 11 Page - Integrated Device Technology

Part No. IDT70V3389S
Description  HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT70V3389S Datasheet(HTML) 11 Page - Integrated Device Technology

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6.42
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
11
tSC
tHC
CE0(B1)
ADDRESS(B1)
A0
A1
A2
A3
A4
A5
tSA
tHA
CLK
4832 drw 07
Q0
Q1
Q3
DATAOUT(B1)
tCH2
tCL2
tCYC2
ADDRESS(B2)
A0
A1
A2
A3
A4
A5
tSA
tHA
CE0(B2)
DATAOUT(B2)
Q2
Q4
tCD2
tCD2
tCKHZ
tCD2
tCKLZ
tDC
tCKHZ
tCD2
tCKLZ
tSC
tHC
tCKHZ
tCKLZ
tCD2
A6
A6
tDC
tSC
tHC
tSC
tHC
An
An + 1
An + 2
An + 3
tCYC2
tCH2
tCL2
R/W
ADDRESS
CE0
CLK
CE1
UB, LB(0-3)
(3)
DATAOUT
OE
tCD2
tCKLZ
Qn
Qn +1
Qn +2
tOHZ
tOLZ
tOE
4832 drw 06
(1)
(1)
tSC
tHC
tSB
tHB
tSW
tHW
tSA
tHA
tDC
tSC
tHC
tSB
tHB
(4)
(1 Latency)
(5)
(5)
T im ing Wa ve for m of a M ult i-Devic e Pipe line d Re a d(1,2)
T im ing Wa ve for m of Re a d Cycle for Pipe line d Ope ra t ion(2)
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB or LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3389 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.


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