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IDT70V3389S Datasheet(PDF) 14 Page - Integrated Device Technology

Part No. IDT70V3389S
Description  HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT70V3389S Datasheet(HTML) 14 Page - Integrated Device Technology

 
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6.42
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
14
ADDRESS
An
D0
tCH2
tCL2
tCYC2
Q0
Q1
0
CLK
DATAIN
R/W
CNTRST
4832 drw 13
INTERNAL
(3)
ADDRESS
ADS
CNTEN
tSRST tHRST
tSD
tHD
tSW tHW
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Qn
An + 1
An + 2
READ
ADDRESS n+1
DATAOUT
tSA tHA
1
An
An + 1
(4)
(5)
(6)
Ax
tSAD tHAD
tSCN tHCN
T im ing Wa ve for m of Writ e w it h Addre ss Count e r Adva nc e (1)
T im ing Wa ve for m of Count e r Re se t (2)
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: ADDR 0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
ADDRESS
An
CLK
DATAIN
Dn
Dn + 1
Dn + 1
Dn + 2
ADS
CNTEN
tCH2
tCL2
tCYC2
4832 drw 12
INTERNAL
(3)
ADDRESS
An
(7)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
tSA
tHA
tSAD tHAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
tSD tHD
tSCN tHCN


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