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P89LPC932A1FA Datasheet(PDF) 2 Page - NXP Semiconductors |
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P89LPC932A1FA Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 64 page 9397 750 14871 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 10 May 2005 2 of 64 Philips Semiconductors P89LPC932A1 8-bit microcontroller with accelerated two-clock 80C51 core s In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. s Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application. s In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application. s Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values. s Low voltage reset (brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt. s Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 µA (total power-down with voltage comparators disabled). s Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available. s Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. s Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. s Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. s Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. s LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip. s Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. s Only power and ground connections are required to operate the P89LPC932A1 when internal reset option is selected. s Four interrupt priority levels. s Eight keypad interrupt inputs, plus two additional external interrupt inputs. s Schmitt trigger port inputs. s Second data pointer. s Emulation support. 2.3 Comparison to the P89LPC932 The P89LPC932A1 includes several improvements compared to the P89LPC932. Please see P89LPC932A1 User manual for additional detailed information. s Byte-erasability has been added to the user code memory space. s All of the errata described in the P89LPC932 Errata sheet have been fixed. s Serial ICP has been added. |
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