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IDT23S08-5HPG Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT23S08-5HPG Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 10 page 4 COMMERCIALANDINDUSTRIALTEMPERATURERANGES IDT23S08 3.3V ZERO DELAY CLOCK MULTIPLIER ZERO DELAY AND SKEW CONTROL To close the feedback loop of the IDT23S08, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are loaded equally, for zero output-output skew. DC ELECTRICAL CHARACTERISTICS - COMMERCIAL Symbol Parameter Conditions Min. Typ.(1) Max. Unit VIL InputLOWVoltageLevel — — 0.8 V VIH Input HIGH Voltage Level 2 — — V IIL InputLOWCurrent VIN = 0V — — 50 µA IIH Input HIGH Current VIN = VDD — — 100 µA VOL OutputLOWVoltage IOL = 8mA (-1, -2, -3, -4) — — 0.4 V IOL = 12mA (-1H, -2H, -5H) VOH Output HIGH Voltage IOH = -8mA (-1, -2, -3, -4) 2.4 — — V IOH = -12mA (-1H, -2H, -5H) IDD_PD Power Down Current REF = 0MHz (S2 = S1 = H) — — 12 µA 100MHz CLKA (-1, -2, -3, -4) — — 45 100MHz CLKA (-1H, -2H, -5H) — — 70 IDD SupplyCurrent UnloadedOutputs 66MHz CLKA (-1, -2, -3, -4) — — 32 mA Select Inputs at VDD or GND 66MHz CLKA (-1H, -2H, -5H) — — 50 33MHz CLKA (-1, -2, -3, -4) — — 18 33MHz CLKA (-1H, -2H, -5H) — — 30 NOTE: 1. Applies to both REF and FBK. Symbol Parameter Test Conditions Min. Max. Unit VDD SupplyVoltage 3 3.6 V TA OperatingTemperature(AmbientTemperature) 0 70 °C CL Load Capacitance below 100MHz — 30 pF Load Capacitance from 100MHz to 133MHz — 15 pF CIN InputCapacitance(1) —7 pF OPERATING CONDITIONS- COMMERCIAL |
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