13

COMMERCIALTEMPERATURERANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 2,048 x 2,048

0123

4

5

6

7

8

9

10

11

12

13

14

15

16

CLK

Offset Value

FE Input

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

GCI Frame

CLK

Offset Value

FE Input

(FD11 = 0, sample at CLK LOW phase)

(FD11 = 1, sample at CLK HIGH phase)

5712 drw07

TABLE 10 — FRAME ALIGNMENT REGISTER (FAR) BITS

Figure 4. Example for Frame Alignment Measurement

Bit

Name

Description

15-13

Unused

Must be zero for normal operation.

12

CFE

When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment

(Complete Frame Evaluation)

offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0.

11

FD11

The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1)

(Frame Delay Bit 11)

or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.

10-0

FD10-0

The binary value expressed in these bits refers to the measured input offset value. These bits are rest to

(Frame Delay Bits)

zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)

Read/Write Address:

Reset Value:

15

14

13

12

11

10

9876543210

0

0

0

CFE

FD11

FD10

FD9

FD8

FD7

FD6

FD5

FD4

FD3

FD2

FD1

FD0