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CAT5409 Datasheet(PDF) 6 Page - Catalyst Semiconductor

Part No. CAT5409
Description  Quad Digitally Programmable Potentiometers (DPPTM) with 64 Taps and 2-wire Interface
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Maker  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
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CAT5409 Datasheet(HTML) 6 Page - Catalyst Semiconductor

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CAT5409
Document No. 2010, Rev. I
SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.
The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
CAT5409 will be considered a slave device in all
applications.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5409 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address of
the particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
0101 for the CAT5409 (see Figure 5). The next four
significant bits (A3, A2, A1, A0) are the device address
bits and define which device the Master is accessing. Up
to sixteen devices may be individually addressed by the
system. Typically, +5V and ground are hard-wired to
these pins to establish the device's address.
After the Master sends a START condition and the slave
address byte, the CAT5409 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT5409 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
8-bit byte.
When the CAT5409 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT5409 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
ACKNOWLEDGE
1
START
SCL FROM
MASTER
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
Figure 4. Acknowledge Timing
5020 FHD F06


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