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TMC5161 Datasheet(PDF) 21 Page - TRINAMIC Motion Control GmbH & Co. KG. |
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TMC5161 Datasheet(HTML) 21 Page - TRINAMIC Motion Control GmbH & Co. KG. |
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21 / 129 page  TMC5161 DATASHEET (Rev. 1.01 / 2018-NOV-20) 21 www.trinamic.com 4.3 Timing The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional 10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the timing parameters of an SPI bus transaction, and the table below specifies their values. CSN SCK SDI SDO tCC tCC tCL tCH bit39 bit38 bit0 bit39 bit38 bit0 tDO tZC tDU tDH tCH Figure 4.1 SPI timing Hint Usually this SPI timing is referred to as SPI MODE 3 SPI interface timing AC-Characteristics clock period: tCLK Parameter Symbol Conditions Min Typ Max Unit SCK valid before or after change of CSN tCC 10 ns CSN high time tCSH *) Min time is for synchronous CLK with SCK high one tCH before CSN high only tCLK*) >2tCLK+10 ns SCK low time tCL *) Min time is for synchronous CLK only tCLK*) >tCLK+10 ns SCK high time tCH *) Min time is for synchronous CLK only tCLK*) >tCLK+10 ns SCK frequency using internal clock fSCK assumes minimum OSC frequency 4 MHz SCK frequency using external 16MHz clock fSCK assumes synchronous CLK 8 MHz SDI setup time before rising edge of SCK tDU 10 ns SDI hold time after rising edge of SCK tDH 10 ns Data out valid time after falling SCK clock edge tDO no capacitive load on SDO tFILT+5 ns SDI, SCK and CSN filter delay time tFILT rising and falling edge 12 20 30 ns |
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