CY62157DV30
MoBL®
Document #: 38-05392 Rev. *E
Page 5 of 12
Data Retention Waveform[15]
Switching Characteristics Over the Operating Range [16]
Parameter
Description
45 ns [13]
55 ns
70 ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
45
55
70
ns
tAA
Address to Data Valid
45
55
70
ns
tOHA
Data Hold from Address Change
10
10
10
ns
tACE
CE1 LOW and CE2 HIGH to Data Valid
45
55
70
ns
tDOE
OE LOW to Data Valid
25
25
35
ns
tLZOE
OE LOW to LOW Z[17]
55
5
ns
tHZOE
OE HIGH to High Z[17, 18]
15
20
25
ns
tLZCE
CE1 LOW and CE2 HIGH to Low Z[17]
10
10
10
ns
tHZCE
CE1 HIGH and CE2 LOW to High Z[17, 18]
20
20
25
ns
tPU
CE1 LOW and CE2 HIGH to Power-Up
0
0
0
ns
tPD
CE1 HIGH and CE2 LOW to Power-Down
45
55
70
ns
tDBE
BLE / BHE LOW to Data Valid
45
55
70
ns
tLZBE
BLE / BHE LOW to Low Z[17]
10
10
10
ns
tHZBE
BLE / BHE HIGH to HIGH Z[17, 18]
15
20
25
ns
Write Cycle[19]
tWC
Write Cycle Time
45
55
70
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
40
40
60
ns
tAW
Address Set-up to Write End
40
40
60
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
35
40
45
ns
tBW
BLE / BHE LOW to Write End
40
40
60
ns
tSD
Data Set-up to Write End
25
25
30
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
WE LOW to High-Z[17, 18]
15
20
25
ns
tLZWE
WE HIGH to Low-Z[17]
10
10
10
ns
Notes:
15. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
16. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedence state.
19. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the write.
VCC, min.
VCC, min.
tCDR
VDR > 1.5 V
DATA RETENTION MODE
tR
CE1 or
VCC
BHE
.BLE
CE2
or
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
