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MSC2383257D Datasheet(PDF) 9 Page - OKI electronic componets

Part No. MSC2383257D
Description  8,388,608-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
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Manufacturer  OKI [OKI electronic componets]
Direct Link  http://www.oki.com
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MSC2383257D Datasheet(HTML) 9 Page - OKI electronic componets

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Semiconductor
MSC2383257D
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles
(/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved.
2. The AC characteristics assumes tT = 2ns.
3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT) are
measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2TTL loads and 100pF.
5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met.
tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then
the access time is controlled by tCAC.
6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met.
tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then
the access time is controlled by tAA.
7. tCEZ(Max.), tREZ(Max.) and tWEZ(Max.) define the time at which the output achieves the open circuit
condition and are not referenced to output voltage levels.
8. tCEZ and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is an 8-bit parallel test function. CA0, CA1 and CA10 are not used. In a read cycle, if all internal bits are
equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low
level. The test mode is cleared and the memory device returned to its normal operating state by a /RAS
only refresh or /CAS before /RAS refresh cycle.
11. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the above value to the specified
value in this data sheet.


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