December 22, 2003
Document No. 38-12009 Rev. *D
75
CY8C22xxx Preliminary Data Sheet
12. Sleep and Watchdog
and f,~01h // disable global interrupts
(prepare for sleep, could be many instructions)
or f,01h // enable global interrupts
mov reg[ffh],08h // Set the sleep bit
Due to the timing of the global interrupt enable instruc-
tion, it is not possible for an interrupt to occur immedi-
ately after that instruction. The earliest the interrupt could
occur is after the next instruction (write to the sleep bit)
has been executed. Therefore, if an interrupt is pending,
the sleep instruction will be executed; but as described in
#1, the sleep instruction will be ignored. The first instruc-
tion executed after the ISR will be the instruction after
sleep.
12.3
Register Definitions
12.3.1
INT_MSK0 Register
The INT_MSK0 register holds bits that are used by several
different resources. The digital clocks only use bit 7 of the
INT_MSK0 register for the VC3 clock and bits zero through
six are used by other resources. The Sleep bit (bit 6) con-
trols whether the Sleep timer may be used as an interrupt
source. For a full discussion of the INT_MSK0 register, see
the Interrupt Controller chapter on page 51.
For additional information, reference the INT_MSK0 register
on page 134.
12.3.2
RES_WDT Register
This write-only register has two functions. A write of any
value will clear the Watchdog Timer. A write of 38h will clear
both the Watchdog Timer (WDT) and the Sleep Timer. It is
important to recall that the WDT is designed to timeout at 3
rollover events of the Sleep Timer. Therefore, if only the
WDT is cleared, the next Watchdog Reset will occur any-
where from two to three times the current Sleep Interval set-
ting. If the Sleep Timer is near the beginning of its count, the
WD timeout will be closer to three times. However, if the
Sleep Timer is very close to its terminal count, the WD time-
out will be closer to two times. To ensure a full three times
timeout, both the WDT and the Sleep Timer may be cleared.
In applications that need a real-time clock, and thus cannot
reset the Sleep Timer when clearing the WDT, the duty cycle
at which the WDT must be cleared should be no greater
than two times of the Sleep Interval.
For additional information, reference the RES_WDT register
on page 137.
12.3.3
OSC_CR0 Register
Bit 7: 32k Select. By default, the 32 kHz clock source is
the Internal Low-Speed Oscillator (ILO). Optionally, the
External Crystal Oscillator (ECO) may be selected.
Bit 6: PLL Mode. This is the only bit in the OSC_CR0 reg-
ister that directly influences the PLL. When set, this bit
enables the PLL. The EXTCLKEN bit in the OSC_CR2 reg-
ister should be set low during PLL operation.
Bit 5: No Buzz. Normally, when the Sleep bit is set in the
CPU_SCR register, all chip systems are powered down,
including the Band Gap reference. However, to facilitate the
detection of POR and LVD events at a rate higher than the
Sleep Interval, the Band Gap circuit is powered up periodi-
cally for about 60 us at the Sleep System Duty cycle (set in
ECO_TR), which is independent of the Sleep Interval and
typically more frequent. When the No Buzz bit is set, the
Sleep System Duty Cycle value is overridden, and the Band
Gap circuit is forced to be on during sleep. This results in
faster response to an LVD or POR event (continuous detec-
tion as opposed to periodic), at the expense of slightly
higher average sleep current.
Bits 4 and 3: Sleep[1:0]. The
available
sleep
interval
selections are shown in Table 12-2. It must be remembered
that when the ILO is the selected 32 kHz clock source, sleep
intervals are approximate.
Bits 2, 1, and 0: CPU Speed[2:0]. The PSoC M8C may
operate over a range of CPU clock speeds (Table 12-3),
allowing the M8C’s performance and power requirements to
be tailored to the application.
The reset value for the CPU Speed bits is zero. Therefore,
the default CPU speed is one-eighth of the clock source.
The internal main oscillator is the default clock source for
the CPU speed circuit; therefore, the default CPU speed is 3
MHz. See “External Clock” on page 254 for more informa-
tion on the supported frequencies for externally supplied
clocks.
The CPU frequency is changed with a write to the
OSC_CR0 register. There are eight frequencies generated
from a power-of-2 divide circuit, which are selected by a 3-
bit code. At any given time, the CPU 8:1 clock multiplexer is
selecting one of the available frequencies, which is re-syn-
chronized to the 24 MHz master clock at the output.
Regardless of the CPU speed bit’s setting, if the actual CPU
speed is greater than 12 MHz, the 24 MHz operating
requirements apply. An example of this scenario is a device
that is configured to use an external clock, which is supply-
ing a frequency of 20 MHz. If the CPU speed register’s
value is 011b, the CPU clock will be 20 MHz. Therefore, the
supply voltage requirements for the device are the same as
if the part was operating at 24 MHz off of the internal main
Table 12-2. Sleep Interval Selections
Sleep Interval
OSC_CR[4:3]
Sleep Timer
Clocks
Sleep Period
(nominal)
Watchdog
Period
(nominal)
00b (default)
64
1.95 ms
6 ms
01b
512
15.6 ms
47 ms
10b
4096
125 ms
375 ms
11b
32,768
1 sec
3 sec
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