December 22, 2003
Document No. 38-12009 Rev. *D
55
6.
General Purpose IO (GPIO)
This chapter discusses the General Purpose IO (GPIO) and its associated registers. The GPIO blocks provide the interface
between the M8C core and the outside world. They offer a large number of configurations to support several types of input/
output operations for both digital and analog systems.
6.1
Architectural Description
The GPIO contains input buffers, output drivers, register bit
storage, and configuration logic for connecting the PSoC
device to the outside world.
IO Ports are arranged with (up to) 8 bits per port. Each full
port contains eight identical GPIO blocks, with connections
to identify a unique address and register bit number for each
block. Therefore, the registers shown in Table 6-1 are actu-
ally for a GPIO port (eight GPIO blocks), where the bit posi-
tion indicates which of the eight GPIO bit blocks is controlled
in the GPIO port.
Each GPIO block can be used for the following types of IO:
s
Digital IO (digital IO controlled by software)
s
Global IO (digital PSoC block IO)
s
Analog IO (analog PSoC block IO)
Each IO pin also has several possible drive modes, as well
as interrupt capabilities. While all GPIO pins are identical
and provide digital IO, some pins may not connect internally
for global or analog functions.
The main block diagram for the GPIO block is illustrated in
Figure 6-1. Note that some pins do not have all of the func-
tionality shown, depending on internal connections.
6.1.1
Digital IO
One of the basic operations of the GPIO ports is to allow the
M8C to send information out of the chip and get information
into the M8C from outside the chip; this is accomplished by
way of the port data register (PRTxDR). Writes from the
M8C to the PRTxDR store the data state, one bit per GPIO.
In the standard non-bypass mode, the pin drivers drive the
pin in response to this data bit, with a drive strength deter-
mined by the drive mode setting (see below). The actual
voltage on the pin depends on the drive mode and the exter-
nal load.
The M8C may read the value of a port by reading the
PRTxDR. When the M8C reads the PRTxDR, the current
value of the pin voltage is translated into a logic value and
returned to the M8C. These operations read the pin voltage,
not the data drive state stored in the local PRTxDR register
bit latch.
6.1.2
Global IO
The GPIO ports are also used to interconnect signals to and
from the digital PSoC blocks, as global inputs or outputs.
The global IO feature of each GPIO (port pin) is off by
default. To access the feature, two parameters must be
changed. To configure a GPIO as a global input the port glo-
bal select bit must be set for the desired GPIO using the
Table 6-1. GPIO Registers
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,xxh
PRTxDR
Data Register
RW : 00
0,xxh
PRTxIE
Bit Interrupt Enables
RW : 00
0,xxh
PRTxGS
Global Select
RW : 00
0,xxh
PRTxDM2
Drive Mode 2
RW : FF
1,xxh
PRTxDM0
Drive Mode 0
RW : 00
1,xxh
PRTxDM1
Drive Mode 1
RW : FF
1,xxh
PRTxIC0
Interrupt Control 0
RW : 00
1,xxh
PRTxIC1
Interrupt Control 1
RW : 00
LEGEND
xx: An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
refer to the “Core Register Summary” on page 32.
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