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XRT71D04 Datasheet(PDF) 3 Page - Exar Corporation

Part No. XRT71D04
Description  4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
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Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
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XRT71D04 Datasheet(HTML) 3 Page - Exar Corporation

 
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XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
I
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
FEATURES ................................................................................................................................................... 1
APPLICATIONS ............................................................................................................................................. 1
Figure 1. Block Diagram (one channel) ................................................................................................. 1
Figure 2. Pin Out of the XRT71D04 ........................................................................................................ 2
ORDERING INFORMATION ..................................................................................................................... 2
TABLE OF CONTENTS...................................................................................................................................... I
PIN DESCRIPTIONS ........................................................................................................... 3
ELECTRICAL CHARACTERISTICS ................................................................................... 9
Figure 3. Input/Output Timing ................................................................................................................ 9
Figure 4. Timing Diagram for the Microprocessor Serial Interface .................................................. 10
SYSTEM DESCRIPTION ................................................................................................... 12
Figure 5. A typical Channel_n of the XRT71D04 configured to operate in the Hardware Mode . 12
Figure 6. A typical Channel_n of the XRT71D04 configured to operate in the Host Mode ........... 13
1.0 Jitter Attenuator PLL .............................................................................................................................. 13
1.1 BACKGROUND INFORMATION ...................................................................................................................................... 13
1.1.1 Definition of Jitter ..........................................................................................................................................13
1.1.2 SONET STS-1 to DS3 Mapping ....................................................................................................................13
1.2 JITTER TRANSFER CHARACTERISTICS......................................................................................................................... 13
Figure 7. Category 1 DS3 Jitter Transfer Mask .................................................................................. 14
1.2.1 Jitter Tolerance ............................................................................................................................................. 14
1.2.2 Jitter Generation............................................................................................................................................ 14
1.2.3 Jitter Attenuation ........................................................................................................................................... 14
1.2.4 SONET STS-1 DS3 Mapping ....................................................................................................................... 14
Figure 8. XRT71D04 Desynchronizer Block Diagram ........................................................................ 15
1.3 XRT71DO4 JITTER TRANSFER CHARACTERISTICS...................................................................................................... 16
TABLE 1: XRT71D04 JITTER TRANSFER FUNCTION .................................................................................. 16
TABLE 2: XRT71D04 MAXIMUM JITTER TOLERANCE ................................................................................. 17
2.0 Operating Modes .................................................................................................................................... 17
2.1 HARDWARE MODE .....................................................................................................................................................17
TABLE 3: FUNCTIONS OF DUAL MODE PINS IN HARDWARE MODE CONFIGURATION ..................................... 17
2.2 HOST MODE:............................................................................................................................................................ 17
TABLE 4: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS ...................................................... 18
3.0 Microprocessor Serial Interface ............................................................................................................ 18
3.1 SERIAL INTERFACE OPERATION.................................................................................................................................. 18
3.1.1 Bit 1—R/W (Read/Write) Bit ..........................................................................................................................18
3.1.2 Bits 2 through 6—A0, A1, A2 ,A3, and A4 .................................................................................................... 18
3.1.3 Bit 7—A5 ....................................................................................................................................................... 18
3.1.4 Bit 8—A6 ....................................................................................................................................................... 18
3.1.5 Read Operation ............................................................................................................................................. 18
3.1.6 Write Operation ............................................................................................................................................. 18
Figure 9. Microprocessor Serial Interface Data Structure ................................................................. 19
3.1.7 Simplified Interface Option ............................................................................................................................ 19
Figure 10. Timing Diagram for the Microprocessor Serial Interface ................................................ 19
ORDERING INFORMATION ............................................................................................. 20
PACKAGE DIMENSIONS ................................................................................................. 20
REVISION HISTORY ..................................................................................................................................... 21


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