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XRT71D04 Datasheet(PDF) 19 Page - Exar Corporation

Part No. XRT71D04
Description  4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
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Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
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XRT71D04 Datasheet(HTML) 19 Page - Exar Corporation

 
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XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
18
3.0
MICROPROCESSOR SERIAL INTERFACE
The serial interface for the XRT71D04 and the
XRT73L00 family of E3/DS3/STS-1 LIU’s are the
same, which makes it easy to configure both the
XRT71D04 and the LIU with a single CS, SDI, SDO
and SClk input and output pins.
3.1
SERIAL INTERFACE OPERATION.
Serial interface data structure and timings are provid-
ed in Figure 5 and 6 respectively.
The clock signal is provided to the SClk and the CS is
asserted for 50 ns prior to the first rising edge of the
SClk.
3.1.1
Bit 1—R/W (Read/Write) Bit
This bit will be clocked into the SDI input, on the first
rising edge of SClk (after CS has been asserted).
This bit indicates whether the current operation is a
Read or Write operation. A “1” in this bit specifies a
Read operation; whereas, a “0” in this bit specifies a
Write operation.
3.1.2
Bits 2 through 6—A0, A1, A2 ,A3, and A4
The five (5) bit Address Values.
The next five rising edges of the SClk signal will clock
in the 5-bit address value for this particular Read (or
Write) operation. The address selects the Command
Register for reading data from, or writing data to. The
address bits to the SDI input pin is applied in ascend-
ing order with the LSB (least significant bit) first.
3.1.3
Bit 7—A5
A5 must be set to “0”, as shown in Figure 9.
3.1.4
Bit 8—A6
The value of A6 is a don’t care.
Once these first 8 bits have been written into the Seri-
al Interface, the subsequent action depends upon
whether the current operation is a Read or Write op-
eration.
3.1.5
Read Operation
Once the last address bit (A4) has been clocked into
the SDI input, the Read operation will proceed
through an idle period, lasting three SClk periods. On
the falling edge of SClk Cycle #8 (see Figure 9) the
serial data output signal (SDO) becomes active. At
this point the user can begin reading the data con-
tents of the addressed Command Register (at Ad-
dress [A4,A3, A2, A1, A0]) via the SDO output pin.
The Serial Interface will output this eight bit data word
(D0 through D7) in ascending order (with the LSB
first), on the falling edges of the SClk . The data (on
the SDO output pin) is stable for reading on the very
next rising edge of the SClk .
3.1.6
Write Operation
Once the last address bit (A4) has been clocked into
the SDI input, the Write operation will proceed
through an idle period, lasting three SClk periods. Pri-
or to the rising edge of SClk Cycle #9 , the eight bit
data word is applied to SDI input. Data on SDI is
latched on the rising edge of SClk.
TABLE 4: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS
ADDR
COMMAND
REGISTER
TYPE
D7
D6
D5
D4
D3
D2
D1
D0
0X06
CR6
R/W
***
***
STS-1_0
DS3/E3_0
DJA_0
RRClkES_0
RClkES_0
FSS_0
0x07
CR7
RO
***
***
***
***
***
***
***
FL_0
0x0E
CR14
R/W
***
***
STS-1_1
DS3/E3_1
DJA_1
RRClkES_1
RClkES_1
FSS_1
0x0F
CR15
RO
***
***
***
***
***
***
***
FL_1
0x16
CR22
R/W
***
***
STS-1_2
DS3/E3_2
DJA_2
RRClkES_2
RClkES_2
FSS_2
0x17
CR23
RO
***
***
***
***
***
***
***
FL_2
0x1E
CR30
R/W
***
***
STS-1_3
DS3/E3_3
DJA_3
RRClkES_3
RCLKES_3
FSS_3
0x1F
CR31
RO
***
***
***
***
***
***
***
FL_3


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