Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

XRT71D04 Datasheet(PDF) 15 Page - Exar Corporation

Part No. XRT71D04
Description  4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
Download  22 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
Logo 

XRT71D04 Datasheet(HTML) 15 Page - Exar Corporation

Zoom Inzoom in Zoom Outzoom out
 15 / 22 page
background image
áç
áç
áç
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
14
1.2.1
Jitter Tolerance
The jitter tolerance in the network element is defined
as the maximum amount of jitter in the incoming sig-
nal that it can receive in an error-free manner.
1.2.2
Jitter Generation
Jitter generation is defined in Section 7.3.3 of GR-
499-CORE. Jitter generation criteria exists for both
Category I and II interfaces, which consist of mapping
and pointer adjustment jitter generation.
Mapping jitter is the sum of the intrinsic payload map-
ping jitter and the jitter that is generated as a result of
the bit stuffing mechnisms used in all of the asynchro-
nous DSn mapping into STS SPE.
1.2.3
Jitter Attenuation
A digital Jitter Attenuation loop combined with the
FIFO provides Jitter attenuation. The Jitter Attenuator
requires no external components except for the refer-
ence clock.
Data is clocked into the FIFO with the associated
clock signal (TClk or RClk) and clocked out of the
FIFO with the dejittered clock and data. When the
FIFO is within 2 bits of being completely full, the FIFO
Limit (FL) will be set.
In Figure 5and Figure 6, this de-jittered clock is la-
beled Smoothed Clock. This Smoothed Clock is now
used to Read Out the Recovered Data from the 16/32
bit FIFO. This Smoothed Clock will also be output to
the Terminal Equipment via the RRClk output pin.
Likewise, the Smoothed Recovered Data will output
to the Terminal Equipment via the RRPOS and
RRNEG output pins.
The XRT71D04 is designed to work as a companion
device with XRT73L04 (STS-1/DS3/E3) Line Inter-
face Unit.
ETSI TBR24 specifies the maximum output jitter in
loop timing must be no more than 0.4UIpp when mea-
sured between 100Hz to 800KHzwith upto 1.5UI input
jitter at 100Hz. This means a jitter attenuator with
bandwidth less than 100Hz is required to be compli-
ant with the standard. ITU G.751 is another applica-
tion where low bandwidth jitter attenuator is needed
to smooth the gapped clock output in the de-multi-
plexer system.
1.2.4
SONET STS-1 DS3 Mapping
Bellcore GR-253 section 3.4.2 and the ANSI T1.105-
199 describes the asynchronous mapping for DS3 in-
to STS-1 SPE.
FIGURE 7. CATEGORY 1 DS3 JITTER TRANSFER MASK
0.1
Acceptable
Range
40
Frequency (Hz)
slope = -20 dB/decade


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn