Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

AD5231 Datasheet(PDF) 3 Page - Analog Devices

Part No. AD5231
Description  Nonvolatile Memory, 1024-Position Digital Potentiometers
Download  24 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

AD5231 Datasheet(HTML) 3 Page - Analog Devices

 
Zoom Inzoom in Zoom Outzoom out
 3 / 24 page
background image
REV. 0
–3–
AD5231
Parameter
Symbol
Conditions
Min
Typ
1
Max
Unit
VW Settling Time
tS
VA = VDD, VB = 0 V,
1.2/3.7/7
µs
VW = 0.50% Error Band,
Code 000H to 200H
For RAB = 10 k
/50 k/100 k
Resistor Noise Voltage
eN_WB
RWB = 5 k
Ω, f = 1 kHz
9
nV/
√Hz
NOTES
1Typicals represent average readings at 25 C and V
DD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. I W ~ 50
µA @ V
DD = +2.7 V and IW ~ 400
µA @ V
DD = +5 V for the RAB = 10 k
version, IW ~ 50 A for the RAB = 50 k
Ω and I
W ~ 25
A for the RAB = 100 k
Ω version. See test circuit Figure 12.
3INL and DNL are measured at V
W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = VSS. DNL
specification limits of –1 LSB minimum are Guaranteed Monotonic operating conditions. See test circuit Figure 13.
4Resistor terminals A, B, and W have no limitations on polarity with respect to each other. Dual Supply Operat ion enables ground-referenced bipolar signal adjustment.
5Guaranteed by design and not subject to production test.
6Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V
DD/2.
7Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 19.
8P
DISS is calculated from (IDD
VDD) + (ISS
VSS).
9All dynamic characteristics use V
DD = +2.5 V and VSS = –2.5 V.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS 10 k , 50 k , 100 k
VERSIONS
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
INTERFACE TIMING
CHARACTERISTICS
2, 3
Clock Cycle Time (tCYC)t1
20
ns
CS Setup Time
t2
10
ns
CLK Shutdown Time to
CS Rise
t3
1tCYC
Input Clock Pulsewidth
t4, t5
Clock Level High or Low
10
ns
Data Setup Time
t6
From Positive CLK Transition
5
ns
Data Hold Time
t7
From Positive CLK Transition
5
ns
CS to SDO-SPI Line Acquire
t8
40
ns
CS to SDO-SPI Line Release
t9
50
ns
CLK to SDO Propagation Delay
4
t10
RP = 2.2 k
Ω, C
L < 20 pF
50
ns
CLK to SDO Data Hold Time
t11
RP = 2.2 k
Ω, C
L < 20 pF
0
ns
CS High Pulsewidth5
t12
10
ns
CS High to CS High5
t13
4tCYC
RDY Rise to
CS Fall
t14
0ns
CS Rise to RDY Fall Time
t15
0.1
0.15
ms
Read/Store to Nonvolatile EEMEM
6
t16
Applies to Command 2H, 3H, 9H
25
ms
CS Rise to Clock Rise/Fall Setup
t17
10
ms
Preset Pulsewidth (Asynchronous)
tPRW
Not Shown in Timing Diagram
50
ms
Preset Response Time to RDY High
tPRESP
PR Pulsed Low to Refreshed
Wiper Positions
70
µs
FLASH/EE MEMORY RELIABILITY
Endurance
7
100
K Cycles
Data Retention
8
100
Years
NOTES
1Typicals represent average readings at 25 C and V
DD = 5 V.
2Guaranteed by design and not subject to production test.
3See timing diagram for location of measured values. All input control voltages are specified with t
R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using both VDD = 3 V and 5 V.
4Propagation delay depends on value of V
DD, RPULL_UP, and CL. See applications text.
5Valid for commands that do not activate the RDY pin.
6RDY pin low only for commands 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_8 ~ 1 s; CMD_9,10 ~0.12 s; CMD_2,3 ~20 s. Device operation at T
A = –40 C
and VDD < +3 V extends the save time to 35 s.
7Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40 C, +25 C, and +85 C; typical endurance at 25 C is 700,000 cycles.
8Retention lifetime equivalent at junction temperature (T
J) = 55 C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
will derate with junction temperature as shown in Figure 20 in the Flash/EE Memory Description section of this data sheet. The AD5231 contains 9,646 transistors.
Die size: 69 mil
115 mil, 7,993 sq. mil.
Specifications subject to change without notice.
(VDD = 3 V to 5.5 V and –40 C < TA < +85 C, unless otherwise noted.)


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn