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AD5231 Datasheet(PDF) 18 Page - Analog Devices |
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AD5231 Datasheet(HTML) 18 Page - Analog Devices |
18 / 24 page REV. 0 AD5231 –18– FLASH/EEMEM RELIABILITY The Flash/EE Memory array on the AD5231 is fully qualified for two key Flash/EE memory characteristics, namely Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many Program, Read, and Erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as: • Initial Page Erase Sequence • Read/Verify Sequence • Byte Program Sequence • Second Read/Verify Sequence During reliability qualification Flash/EE memory is cycled from 000H to 3FFH until a first fail is recorded signifying the endurance limit of the on-chip Flash/EE memory. As indicated in the specification pages of this data sheet, the AD5231 Flash/EE Memory Endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of –40 °C to +85°C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25 °C. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the AD5231 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 55 °C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit described above, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash/EE memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 eV, will derate with TJ as shown in Figure 20. For example, the data is retained for 100 years at 55 °C operation, but reduces to 15 years at 85 °C operation. Beyond such limit, the part must be reprogrammed so that the data can be restored. TJ JUNCTION TEMPERATURE – C 300 250 0 40 200 150 100 50 50 60 70 80 90 100 110 ADI TYPICAL PERFORMANCE AT TJ = 55 C Figure 20. Flash/EE Memory Data Retention APPLICATIONS Bipolar Operation From Dual Supplies The AD5231 can be operated from dual supplies ±2.5 V, which enables control of ground referenced ac signals or bipolar operation. AC signal, as high as VDD/VSS, can be applied directly across terminals A-B with output taking from terminal W. (See Figure 21 for a typical circuit connection.) 2.5V p-p AD5231 VSS GND SDI CLK SS SCLK MOSI GND VDD C 1.25V p-p VDD +2.5V –2.5V CS D = MIDSCALE A W B Figure 21. Bipolar Operation from Dual Supplies High Voltage Operation The Digital Potentiometer can be placed directly in the feedback or input path of an op amp for gain control, provided that the voltage across terminals A-B, W-A, or W-B does not exceed |5 V|. When high voltage gain is needed, users should set a fixed gain in an op amp operated at +15 V, and let the digital potentiometer control the adjustable input. Figure 22 shows a simple implementation. R2R 5V AD5231 A W B 15V V+ V– VO 0 TO 15V A1 – + Figure 22. 15 V Voltage Span Control Bipolar Programmable Gain Amplifier There are several ways to achieve bipolar gain. Figure 23 shows one versatile implementation. Digital potentiometer U1 sets the adjustment range, the wiper voltage VW2 can therefore be programmed between Vi and –KVi at a given U2 setting. For linear adjustment, configure A2 as a noninverting amplifier and the trans- fer function becomes: V V R R D KK O i =+ ×× + () 1 2 1 1024 1 2 – (4) where: K is the ratio of RWB/RWA which is set by U1. D = Decimal Equivalent of the Input Code |
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