A25L80P datasheet(14/34 Pages) AMICC

Part #	A25L80P

Description	8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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A25L80P

PRELIMINARY

(May 2005, Version 0.0)

13

AMIC Technology Corp.

Read Data Bytes (READ)

The device is first selected by driving Chip Select ( S ) Low. The

instruction code for the Read Data Bytes (READ) instruction is

followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the

memory contents, at that address, is shifted out on Serial Data

Output (Q), each bit being shifted out, at a maximum frequency

fR, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 8. The first byte

addressed can be at any location. The address is automatically

incremented to the next higher address after each byte of data

is shifted out. The whole memory can, therefore, be read with a

single Read Data Bytes (READ) instruction. When the highest

address is reached, the address counter rolls over to 000000h,

allowing the read sequence to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by

driving Chip Select ( S ) High. Chip Select ( S ) can be driven

High at any time during data output. Any Read Data Bytes

(READ) instruction, while an Erase, Program or Write cycle is

in progress, is rejected without having any effects on the cycle

that is in progress.

Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

S

C

D

Q

Instruction

High Impedance

MSB

810

9

01 2 3 4

5 6 7

Data Out 1

Data Out 2

24-Bit Address

28 29 30 31 32 33 34 35 36 37 38 39

23 22 21

3 21 0

7

6 54 32 10

7

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