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LDS8868 Datasheet(PDF) 3 Page - IXYS Corporation

Part No. LDS8868
Description  6-Channel Ultra Low Dropout LED Driver
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Maker  IXYS [IXYS Corporation]
Homepage  http://www.ixys.com
Logo IXYS - IXYS Corporation

LDS8868 Datasheet(HTML) 3 Page - IXYS Corporation

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LDS8868
© 2009 IXYS Corp.
3
Doc. No. 8868_DS, Rev. N2.1
Characteristics subject to change without notice
RECOMMENDED EN/SET TIMING
For 2.7
V
IN 5.5V, over full ambient temperature range - 40 to +85ºC.
Symbol
Name
Conditions
Min
Typ
Max
Units
tSETUP
EN/SET setup from shutdown
10
100
μs
tLO
EN/SET program low time
0.2
100
μs
tHI
EN/SET program high time
0.2
100
μs
tOFF
EN/SET low time to shutdown
1.5
ms
tDATADELAY
EN/SET Delay to DATA
500
μs
tRESETDELAY
EN/SET Delay High to ADDRESS
2
ms
Figure 1. EN/SET One Wire Addressable Timing Diagram
REGISTER CONFIGURATION AND PROGRAMMING
Table 1. Register Address and Data
DATA pattern
Register
Address
Pulses
Description
Bits
Bit 3
Bit 2
Bit 1
Bit 0
REG1
1
Bank Enable and IMODE
4
IMODE
ENC
ENB
ENA
REG2
2
Global Current Setting*
6
REG3
3
Bank C Current Setting
6
REG4
4
Bank B Current Setting
6
REG5
5
Bank A Current Setting
6
See Table 3 for values
REG6
6
Return to 1x mode
1
RTRN
Note: *) If Global current setting register Reg2 is used, registers Reg3 – Reg5 should be empty, and vice versa If registers Reg3 – Reg5 are
used, Reg2 should be empty to prevent data interference.
Table 2. Reg1 Code
Reg1 Bit
Reg1 Bit
Reg1 Bit
Data
pulses
3
2
1
0
Data
pulses
3
2
1
0
Data
pulses
3
2
1
0
0
0
0
0
0
6
1
0
1
0
12
0
1
0
0
1
1
1
1
1
7
1
0
0
1
13
0
0
1
1
2
1
1
1
0
8
1
0
0
0
14
0
0
1
0
3
1
1
0
1
9
0
1
1
1
15
0
0
0
1
4
1
1
0
0
10
0
1
1
0
16
0
0
0
0
5
1
0
1
1
11
0
1
0
1
Note: If bits Bit0 – Bit2 are set to zero, the corresponding LED bank is disabled.


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