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8N4DV01EG-0000CDI8 Datasheet(PDF) 4 Page - Integrated Device Technology |
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8N4DV01EG-0000CDI8 Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 20 page IDT8N4QV01GCD REVISION A MARCH 11, 2014 4 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Block Diagram with Programming Registers Q nQ OSC 114.285 MHz PFD & LPF FemtoClock® NG VCO 1950-2600MHz ÷ N I2C Control VC SCLK SDATA FSEL[1:0] OE Pullup Pullup Pulldown, Pulldown Pullup Feedback Divider M (25 Bit) MINT (7 bits) MFRAC (18 bits) Programming Registers ADC_GAIN ADC_POL I2C: 6 bits 1 bit Def: 6 bits 1 bit P0 MINT0 MFRAC0 N0 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P1 MINT1 MFRAC1 N1 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P2 MINT2 MFRAC2 N2 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P3 MINT3 MFRAC3 N3 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits Def: Power-up default register setting for I2C registers 00 01 10 11 34 34 34 34 34 7 34 7 30 30 30 30 18 Output Divider N A/D 7 ADC_GAINn, ADC_POL, Pn, MINTn, MFRACn and Nn 7 7 41 ÷P 2 |
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