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8N4Q003BG-0000CDI8 Datasheet(PDF) 3 Page - Integrated Device Technology |
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8N4Q003BG-0000CDI8 Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 21 page IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO IDT8N3Q001GCD REVISION A MARCH 6, 2012 3 ©2012 Integrated Device Technology, Inc. Block Diagram with Programming Registers Q nQ OSC fXTAL PFD & LPF FemtoClock® NG VCO 1950-2600MHz ÷ N I2C Control SCLK SDATA FSEL[1:0] OE Pullup Pullup Pulldown Pullup Feedback Divider M (25 Bit) MINT (7 bits) MFRAC (18 bits) Programming Registers P0 MINT0 MFRAC0 N0 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P1 MINT1 MFRAC1 N1 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P2 MINT2 MFRAC2 N2 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P3 MINT3 MFRAC3 N3 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits Def (default): Power-up default register setting for I2C registers 00 01 10 11 34 34 34 34 34 7 27 7 30 30 30 30 18 Output Divider N Pn, MINTn, MFRACn and Nn 34 ÷P 2 2 |
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