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SC16C652B Datasheet(PDF) 1 Page - NXP Semiconductors

Part No. SC16C652B
Description  5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SC16C652B Datasheet(HTML) 1 Page - NXP Semiconductors

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with
32-byte FIFOs and infrared (IrDA) encoder/decoder
Rev. 03 — 10 December 2004
Product data
The SC16C652B is a 2 channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert
parallel data into serial data and vice versa. The UART can handle serial data rates
up to 5 Mbit/s. The SC16C652B is pin compatible with the SC16C2550. It will
power-up to be functionally equivalent to the 16C2450. The SC16C652B provides
enhanced UART functions with 32-byte FIFOs, modem control interface, DMA mode
data transfer, and IrDA encoder/decoder. The DMA mode data transfer is controlled
by the FIFO trigger levels and the TXRDY and RXRDY signals. On-board status
registers provide the user with error indications and operational status. System
interrupts and modem control features may be tailored by software to meet specific
user requirements. An internal loop-back capability allows on-board diagnostics.
Independent programmable baud rate generators are provided to select transmit and
receive baud rates.
The SC16C652B operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature
range, and is available in plastic LQFP48 and very small (Micro-UART) HVQFN32
s 2 channel UART
s 5 V, 3.3 V and 2.5 V operation
s 5 V tolerant inputs
s Industrial temperature range (
−40 °C to +85 °C)
s Pin and functionally compatible to 16C2450 in LQFP48 package, and software
compatible with industry standard 16C450, 16C550, and SC16C650
s Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
s 32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
s 32-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
s Independent transmit and receive UART control
s Four selectable Receive and Transmit FIFO interrupt trigger levels
s Automatic software (Xon/Xoff) and hardware (RTS/CTS) flow control
s Programmable Xon/Xoff characters
s Software selectable Baud Rate Generator
s Standard modem interface or infrared IrDA encoder/decoder interface
s Supports IrDA version 1.0 (up to 115.2 kbit/s)
s Sleep mode

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