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SC16C652B Datasheet(PDF) 5 Page - NXP Semiconductors |
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SC16C652B Datasheet(HTML) 5 Page - NXP Semiconductors |
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5 / 44 page 
Philips Semiconductors SC16C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Product data Rev. 03 — 10 December 2004 5 of 44 9397 750 14452 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 5.2 Pin description Table 2: Pin description Symbol Pin Type Description LQFP48 HVQFN32 A0 28 19 I Address 0 select bit. Internal register address selection. A1 27 18 I Address 1 select bit. Internal register address selection. A2 26 17 I Address 2 select bit. Internal register address selection. CSA, CSB 10, 11 8, 9 I Chip Select A, B (Active-LOW). This function is associated with individual channels, A through B. These pins enable data transfers between the user CPU and the SC16C652B for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic 0 on the respective CSA, CSB pin. D0-D7 44-48, 1-3 27-32, 1-2 I/O Data bus (bi-directional). These pins are the 8-bit, 3-State data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. GND 17 13 I Signal and power ground. INTA, INTB 30, 29 21, 20 O Interrupt A, B (3-State). This function is associated with individual channel interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and is active when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. IOR 19 14 I Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load the contents of an internal register defined by address bits A0-A2 onto the SC16C652B data bus (D0-D7) for access by external CPU. IOW15 12 I Write strobe (Active-LOW strobe). A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2. OP2A, OP2B 32, 9 22, 7 O Output 2 (user-defined). This function is associated with individual channels, A through B. The state at these pin(s) are defined by the user and through MCR register bit 3. INTA, INTB are set to the active mode and OP2 to logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the 3-State mode and OP2 to a logic 1 when MCR[3] is set to a logic 0. See bit 3, Modem Control Register (MCR[3]). Since these bits control both the INTA, INTB operation and OP2 outputs, only one function should be used at one time, INT or OP2. RESET 36 24 I Reset (Active-HIGH). A logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See Section 7.11 “SC16C652B external reset condition” for initialization details.) RXRDYA, RXRDYB 31, 18 - O Receive Ready A, B (Active-LOW). This function provides the RX FIFO/RHR status for individual receive channels (A-B). RXRDYn is primarily intended for monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0 indicates there is a receive data to read/upload, i.e., receive ready status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level has not been reached. This signal can also be used for single mode transfers (DMA mode 0). |
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