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MC1451A Datasheet(PDF) 66 Page - List of Unclassifed Manufacturers |
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MC1451A Datasheet(HTML) 66 Page - List of Unclassifed Manufacturers |
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66 / 70 page  66 16-bit Parallel DAC Interface The Interface between the MC1231A chip set and one or more 16 bit DACs is shown in the following figure. Comments on Schematic The 16 Data bits and 2 address bits from the CP chip are latched in the two 74FCT841 latches when the CP writes to address F hex, in the address bits A0:A3. Three 74C373 latches could also be used. If this is a write to the DAC, DACSLCT will be asserted during this CP bus cycle. The assertion of DACSLCT will be latched by the fed-back and-or gate and the next clock will set the DACWR flop. The second clock will set the second shift flop which will clear the DACL latch. Since this latch has been cleared the third clock will clear DACWR providing a two clock DACWR level. The fourth clock will clear the second shift flop returning the system to its original state waiting for the next DACSLCT. The DACWR assertion will enable the decoder causing the DAC selected by the address bits stored in the transparent latch. The timing described will produce a two clock write pulse to the DACs. This will be about 320 nSec using I/OClk. |
Similar Part No. - MC1451A |
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Similar Description - MC1451A |
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