Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MSC1162A Datasheet(PDF) 6 Page - OKI electronic componets

Part No. MSC1162A
Description  40-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver
Download  14 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  OKI [OKI electronic componets]
Homepage  http://www.oki.com
Logo 

MSC1162A Datasheet(HTML) 6 Page - OKI electronic componets

Zoom Inzoom in Zoom Outzoom out
 6 / 14 page
background image
¡ Semiconductor
MSC1162A
6/14
PIN DESCRIPTION
Symbol
Description
CLK
Shift register clock input pin.
Shift register reads data through DIN while the CLK pin is low state and the data in the shift
register is shifted from one stage to the next stage at the rising edge of the clock.
Type
I
Serial data input pin of the shift register.
Display data (positive logic) is input in through the DIN pin synchronization with clock.
DIN
I
Serial data output pin of the shift register.
Data is output through the DOUT pin in synchronization with the CLK signal.
When R/L = High, the data of PO40 in the shift register is output through the DOUT pin.
When R/L = Low, the data of PO1 pin in the shift register is output through the DOUT pin.
DOUT
O
Latch strobe input pin
When LS is high, the parallel output data (PO1-40) of the shift register read out. When LS
goes from high to low, the parallel output data (PO1-40) of the shift register is held.
LS
I
Clear input pin with a built-in pull-up resistor
The CL pin is normally being set high.
If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV40) are in phase
with the corresponding latch outputs (O1 to O40).
If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV40) are high
irrespective of the states of the latch outputs.
If the CL pin is set low, the driver outputs are driven low irrespective of the states of the
CHG pin and latch outputs.
This allows display blanking to be set.
CL
I
Input for testing (with a pull-down resistor)
The CL pin is normally being set low.
If the CHG pin is low and the CL pin is high, the driver outputs (HV01 to HV40) are in phase
with the corresponding latch outputs (O1 to O40).
If the CHG pin is low and the CL pin is low, the driver outputs (HV01 to HV40) are low
irrespective of the states of the latch outputs.
If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the
latch outputs.
This provides the easy testing of all lights after final assembly.
CHG
I
High voltage driver outputs for driving VFD tube
The driver outputs are in phase with the corresponding latch outputs (O1 to O40).
The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors.
VHO1-40
O
Power supply pin for driver circuits of VFD tube
VHV
Power supply pin for logic
VCC
GND pin for driver circuits of a VFD tube. (D-GND)
Since the GND1 is not be connected to L-GND, connect this pin to the external L-GND.
GND1
GND pin for the logic circuits. (L-GND)
Since the GND2 pin is not be connected to D-GND, connect this pin to the external D-GND.
GND2


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn