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IDT74LVC374A Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT74LVC374A Datasheet(HTML) 1 Page - Integrated Device Technology |
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INDUSTRIALTEMPERATURERANGE IDT74LVC374A 3.3VCMOSOCTALEDGE-TRIGGEREDD-TYPEFLIP-FLOP 1 APRIL 1999 INDUSTRIAL TEMPERATURE RANGE The IDT logo is a registered trademark of Integrated Device Technology, Inc. © 1999 Integrated Device Technology, Inc. DSC-4618/2 FEATURES: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) •VCC = 3.3V ± 0.3V, Normal Range •VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4 µµµµµ W typ. static) • Rail-to-rail output swing for increased noise margin • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SOIC, SSOP, QSOP, and TSSOP packages FUNCTIONAL BLOCK DIAGRAM APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise IDT74LVC374A DESCRIPTION: The LVC374A octal edge triggered D-type flip-flop is built using advanced dualmetalCMOStechnology.Thisdevicefeatures3-stateoutputsdesigned specifically for driving highly capacitive or relatively low-impedance loads. The LVC374A device is particularly suitable for implementing buffer regis- ters, input-output (I/O) ports, bidirectional bus drivers, and working regis- ters. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. Abufferedoutput-enable(OE)inputcanbeusedtoplacetheeightoutputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The LVC374A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows theuseofthisdeviceasatranslatorinamixed3.3V/5Vsystemenvironment. 3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP- FLOP WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O OE C1 CLK 1 D TO SEVEN OTHER CHANNELS 1 11 3 2 1 D 1 Q |
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