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ML9261 Datasheet(PDF) 6 Page - OKI electronic componets

Part No. ML9261
Description  60-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver
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Maker  OKI [OKI electronic componets]
Homepage  http://www.oki.com
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ML9261 Datasheet(HTML) 6 Page - OKI electronic componets

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¡ Semiconductor
ML9261/62
6/16
PIN DESCRIPTION
Symbol
Description
CLK
Shift register clock input pin.
Shift register reads data from DIN while the CLK pin is low and the data in the shift register
is shifted from one stage to the next stage at the rising edge of the clock.
Type
I
Serial data input pin of the shift register.
Display data (positive logic) is input in the DIN pin in synchronization with clock.
DIN
I
Serial data output pin of the shift register.
Data is output from the DOUT pin in synchronization with the CLK signal.
DOUT
O
Latch strobe input pin.
The contents of the parallel outputs (PO1 to PO60) of the shift register are read at the rising
edge of LS (edge-triggered). When the CLK rises while LS is high, the parallel outputs
(PO1 to PO60) and latch outputs (O1 to O60) go low.
LS
I
Clear input pin with a built-in pull-down resistor.
The CL pin is normally set high.
If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV60) are in phase
with the corresponding register outputs (O1 to O60).
If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV60) are high
irrespective of the states of the register outputs.
If the CL pin is set low, the driver outputs are driven low irrespective of the states of the
CHG pin and register outputs.
This allows display blanking to be set.
CL
I
Input for testing (with a pull-down resistor).
The CL pin is normally set low.
If the CHG pin is low and the CL pin is high, the driver outputs (HV01 to HV60) are in phase
with the corresponding register outputs (O1 to O60).
If the CHG pin is low and the CL pin is low, the driver outputs (HV01 to HV60) are low
irrespective of the states of the register outputs.
If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the
register outputs.
This provides the easy testing of all lights after final assembly.
CHG
I
High voltage driver outputs for driving VFD tube.
If the CL pin is high and the CHG pin is low, the driver outputs are in phase with the
corresponding register outputs (O1 to O60).
The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors.
VHO1-60
O
Power supply pin for driver circuits of VFD tube
VDISP
Power supply pin for logic
VDD
GND pin for driver circuits of a VFD tube.
Since the D-GND is not be connected to L-GND, connect this pin to the external L-GND.
D-GND
GND pin for the logic circuits.
Since the L-GND pin is not be connected to D-GND, connect this pin to the external D-GND.
L-GND


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