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MAX1195 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX1195 Datasheet(HTML) 5 Page - Maxim Integrated Products |
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5 / 22 page 
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs _______________________________________________________________________________________ 5 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) CLK 0.8 × VDD Input High Threshold VIH PD, OE, SLEEP, T/B 0.8 × OVDD V CLK 0.2 × VDD Input Low Threshold VIL PD, OE, SLEEP, T/B 0.2 × OVDD V Input Hysteresis VHYST 0.15 V IIH VIH = VDD = OVDD ±20 Input Leakage IIL VIL = 0 ±20 µA Input Capacitance CIN 5pF DIGITAL OUTPUTS ( D7A–D0A, D7B–D0B) Output Voltage Low VOL ISINK = -200µA 0.2 V Output Voltage High VOH ISOURCE = 200µA OVDD - 0.2 V Three-State Leakage Current ILEAK OE = OVDD ±10 µA Three-State Output Capacitance COUT OE = OVDD 5pF POWER REQUIREMENTS Analog Supply Voltage Range VDD 2.7 3 3.6 V Output Supply Voltage Range OVDD CL = 15pF 1.7 3 3.6 V Operating, fINA & B = 20MHz at -1dB FS applied to both channels 29 36 Sleep mode 3 mA Analog Supply Current IVDD Shutdown, clock idle, PD = OE = OVDD 0.1 20 µA Operating, fINA & B = 20MHz at -1dB FS applied to both channels (Note 6) 8mA Sleep mode 3 Output Supply Current IOVDD Shutdown, clock idle, PD = OE = OVDD 310 µA Operating, fINA & B = 20MHz at -1dB FS applied to both channels 87 108 Sleep mode 9 mW Analog Power Dissipation PDISS Shutdown, clock idle, PD = OE = OVDD 0.3 60 µW Offset, VDD ±5% ±3 Power-Supply Rejection PSRR Gain, VDD ±5% ±3 mV/V ELECTRICAL CHARACTERISTICS (continued) (VDD = OVDD = 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k Ω resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characerization. Typical values are at TA = +25°C.) |
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