K9F1216D0A-Y datasheet(7/46 Pages) SAMSUNG

Part #	K9F1216D0A-Y

Description	64M x 8 Bit , 32M x 16 Bit NAND Flash Memory

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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FLASH MEMORY

7

K9F1208D0A

K9F1208U0A

K9F1216D0A

K9F1216U0A

512Byte

16 Byte

Figure 1-1. K9F1208X0A (X8) FUNCTIONAL BLOCK DIAGRAM

Figure 2-1. K9F1208X0A (X8) ARRAY ORGANIZATION

VCC

X-Buffers

512M + 16M Bit

Command

NAND Flash

ARRAY

(512 + 16)Byte x 131072

Y-Gating

Page Register & S/A

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

VSS

A9 - A25

A0 - A7

Command

CE

RE

WE

WP

I/0 0

I/0 7

VCC/VCCQ

VSS

A8

1st half Page Register

(=256 Bytes)

2nd half Page Register

(=256 Bytes)

128K Pages

(=4,096 Blocks)

512 Byte

8 bit

16 Byte

1 Block =32 Pages

= (16K + 512) Byte

I/O 0 ~ I/O 7

1 Page = 528 Byte

1 Block = 528 Byte x 32 Pages

= (16K + 512) Byte

1 Device = 528Bytes x 32Pages x 4096 Blocks

= 528 Mbits

Column Address

Row Address

(Page Address)

Page Register

CLE ALE

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.

01h Command(Read) : Defines the starting address of the 2nd half of the register.

* A8 is set to "Low" or "High" by the 00h or 01h Command.

* L must be set to "Low".

* The device ignores any additional input of address cycles than reguired.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

1st Cycle

A0

A1

A2

A3

A4

A5

A6

A7

2nd Cycle

A9

A10

A11

A12

A13

A14

A15

A16

3rd Cycle

A17

A18

A19

A20

A21

A22

A23

A24

4th Cycle

A25

*L

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K9F1216D0A-Y Datasheet(PDF) 7 Page - Samsung semiconductor

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