FLASH MEMORY

7

K9E2G08U0M

Preliminary

Product Introduction

The K9E2G08U0M is a 2,112Mbits(2,214,592,512 bits) memory organized as 524,288 rows(pages) by 528 columns. Spare sixteen

columns are located from column address of 512 to 527. A 528-bytes data register is connected to memory cell arrays accommodat-

ing data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up

of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of

the 32 pages formed two NAND structures. A NAND structure consists of 16 cells. Total 1,056 NAND structures reside in a block. The

array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is

executed on a block basis. The memory array consists of 16,384 separately erasable 16K-bytes blocks. It indicates that the bit by bit

erase operation is prohibited on the K9E2G08U0M.

The K9E2G08U0M has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems

upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through

I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address

Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 256M byte physical space requires

28 addresses, thereby requiring four cycles for byte-level addressing : 1 cycle of column address, 3 cycles of row address, in that

order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-

ation, however, only the 3 cycles of row address are used. Device operations are selected by writing specific commands into the com-

mand register. Table 1 defines the specific commands of the K9E2G08U0M.

The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into eight 256Mbit

separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining

the conventional 512 bytes structure. The extended pass/fail status for multi-plane program/erase allows system software to quickly

identify the failing page/block out of selected multiple pages/blocks. Usage of multi-plane operations will be described further through-

out this document.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another

of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burst-

reading and data-input cycles are removed, system performance for solid-state disk application is significantly increased.

The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide

identification capabilities. Detailed information can be obtained by contact with Samsung.

Table 1. Command Sets

NOTE : 1. The 00h/01h command defines starting address of the 1st/2nd half of registers.

After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h)

on the next cycle.

2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation.

Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd, 3rd, 4th plane of multi-plane operation.

3. The 71h command should be used for read status of Multi Plane operation.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

Function

1’st Cycle

2’nd

Cycle

3’rd

Cycle

4’th Cycle

5’th Cycle

Acceptable Command

during Busy

Read 1

---

-

Read 2

50h

-

-

-

-

Read ID

90h/91h

-

-

-

-

Reset

FFh

---

-

O

80h

10h

-

-

-

80h

11h

-

-

-

00h

8Ah

10h

-

-

03h

8Ah

11h

-

-

Block Erase

60h

D0h

-

-

-

Multi-Plane Block Erase

60h----60h

D0h

-

-

-

Read Status

70h

-

-

-

-

O

Read Multi-Plane Status

---

-

O