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IS61LV12824 Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc

Part No. IS61LV12824
Description  128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY
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Maker  ISSI [Integrated Silicon Solution, Inc]
Homepage  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS61LV12824 Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc

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IS61LV12824
ISSI®
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. D
06/22/05
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
FEATURES
• High-speed access time: 8, 10 ns
• CMOS low power operation
— 756 mW (max.) operating @ 8 ns
— 36 mW (max.) standby @ 8 ns
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Available in 119-pin Plastic Ball Grid Array
(PBGA) and 100-pin TQFP packages.
• Industrial temperature available
• Lead-free available
DESCRIPTION
The
ISSI IS61LV12824 is a high-speed, static RAM organized
as 131,072 words by 24 bits. It is fabricated using
ISSI's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 8 ns with low power consumption.
When
CE1, CE2 are HIGH and CE2 is LOW (deselected), the
device assumes a standby mode at which the power dissipa-
tion can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE1, CE2, CE2 and OE. The active
LOW Write Enable (
WE) controls both writing and reading of
the memory.
The IS61LV12824 is packaged in the JEDEC standard
119-pin PBGA and 100-pin TQFP.
FUNCTIONAL BLOCK DIAGRAM
JUNE 2005
A0-A16
CE1
OE
WE
128K x 24
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
CE2
CE2
I/O0-I/O23
128K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY


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