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DS33ZH11 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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DS33ZH11 Datasheet(HTML) 5 Page - Maxim Integrated Products |
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5 / 169 page  DS33Z11 Ethernet Mapper 5 of 169 LIST OF FIGURES Figure 3-1 Ethernet to WAN Extension (No Framing) ..............................................................................................11 Figure 3-2 Ethernet to WAN Extension (T1E1 Framing and LIU) ............................................................................12 Figure 3-3 Ethernet to WAN Extension with T3/E3 Framing ....................................................................................12 Figure 3-4 Ethernet over DSL...................................................................................................................................13 Figure 3-5 Copper to Fiber Connection ....................................................................................................................13 Figure 6-1 Detailed Block Diagram...........................................................................................................................16 Figure 7-1 DS33Z11 169-Ball CSBGA Pinout ..........................................................................................................27 Figure 7-2 DS33ZH11 100-Ball CSBGA Pinout (Hardware or SPI Mode Only) .......................................................28 Figure 8-1 Clocking for the DS33Z11 .......................................................................................................................32 Figure 8-2 Device Interrupt Information Flow Diagram.............................................................................................37 Figure 8-3 Flow Control Using Pause Control Frame...............................................................................................42 Figure 8-4 IEEE 802.3 Ethernet Frame ....................................................................................................................43 Figure 8-5 Configured as DTE Connected to an Ethernet PHY in MII Mode............................................................45 Figure 8-6 DS33Z11 Configured as a DCE in MII Mode ..........................................................................................46 Figure 8-7 RMII Interface..........................................................................................................................................48 Figure 8-8 MII Management Frame..........................................................................................................................49 Figure 8-9 PRBS Synchronization State Diagram ....................................................................................................51 Figure 8-10 Repetitive Pattern Synchronization State Diagram ...............................................................................52 Figure 8-11 LAPS Encoding of MAC Frames Concept.............................................................................................56 Figure 8-12 X.86 Encapsulation of the MAC field.....................................................................................................57 Figure 8-13 CIR in the WAN Transmit Path .............................................................................................................60 Figure 10-1 TX Serial Interface Functional Timing .................................................................................................139 Figure 10-2 RX Serial Interface Functional Timing.................................................................................................139 Figure 10-3 Transmit Byte Sync Functional timing .................................................................................................140 Figure 10-4 Receive Byte Sync Functional Timing .................................................................................................140 Figure 10-5 MII Transmit Functional Timing...........................................................................................................141 Figure 10-6 MII Transmit Half Duplex with a Collision Functional Timing ..............................................................141 Figure 10-7 MII Receive Functional Timing ............................................................................................................141 Figure 10-8 RMII Transmit Interface Functional Timing .........................................................................................141 Figure 10-9 RMII Receive Interface Functional Timing ..........................................................................................142 Figure 10-10 SPI Master Functional Timing ...........................................................................................................142 Figure 11-1 Transmit MII Interface .........................................................................................................................146 Figure 11-2 Receive MII Interface Timing...............................................................................................................147 Figure 11-3 Transmit RMII Interface.......................................................................................................................148 Figure 11-4 Receive RMII Interface Timing............................................................................................................149 Figure 11-5 MDIO Timing .......................................................................................................................................150 Figure 11-6 Transmit WAN Timing.........................................................................................................................151 Figure 11-7 Receive WAN timing ...........................................................................................................................152 Figure 11-8 SDRAM Interface Timing.....................................................................................................................154 Figure 11-9 Intel Bus Read Timing (HWMODE = 0, MODEC = 00) .......................................................................156 Figure 11-10 Intel Bus Write Timing (HWMODE = 0, MODEC = 00) .....................................................................156 Figure 11-11 Motorola Bus Read Timing (HWMODE = 0, MODEC = 01)..............................................................157 Figure 11-12 Motorola Bus Write Timing (HWMODE = 0, MODEC = 01)..............................................................157 Figure 11-13 EEPROM Interface Timing................................................................................................................158 Figure 11-14 JTAG Interface Timing Diagram........................................................................................................159 Figure 12-1 JTAG Functional Block Diagram .........................................................................................................160 Figure 12-2 TAP Controller State Diagram.............................................................................................................163 Figure 12-3 JTAG Functional Timing......................................................................................................................166 |
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