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S1D13706 Datasheet(PDF) 40 Page - Epson Company

Part # S1D13706
Description  S1D13706 Embedded Memory LCD Controller
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Manufacturer  EPSON [Epson Company]
Direct Link  http://www.epsondevice.com
Logo EPSON - Epson Company

S1D13706 Datasheet(HTML) 40 Page - Epson Company

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Page 40
Epson Research and Development
Vancouver Design Center
S1D13706
Hardware Functional Specification
X31B-A-001-09
Issue Date: 2004/02/09
1.
t15 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note
Minimum one software WAIT state is required.
Table 6-7: Hitachi SH-4 Interface Timing
Symbol
Parameter
2.0V
3.3V
Unit
Min
Max
Min
Max
fCKIO
Clock frequency
20
66
MHz
TCKIO
Clock period
1/fCKIO
1/fCKIO
ns
t1
Clock pulse width low
22.5
6.8
ns
t2
Clock pulse width high
22.5
6.8
ns
t3
A[16:1], M/R#, RD/WR# setup to CKIO
01
ns
t4
A[16:1], M/R#, RD/WR# hold from CSn#
00
ns
t5
BS# setup
31
ns
t6
BS# hold
72
ns
t7
CSn# setup
01
ns
t8
CSn# high setup to CKIO
02
ns
t9a
RD# or WEn# asserted for MCLK = BCLK (max. MCLK = 50MHz)
8.5
8.5
TCKIO
t9b
RD# or WEn# asserted for MCLK = BCLK
÷ 2
11.5
11.5
TCKIO
t9c
RD# or WEn# asserted for MCLK = BCLK
÷ 3
13.5
13.5
TCKIO
t9d
RD# or WEn# asserted for MCLK = BCLK
÷ 4
18.5
18.5
TCKIO
t10
Falling edge RD# to D[15:0] driven (read cycle)
5243
12
ns
t11
Falling edge CSn# to RDY# driven high
3193
12
ns
t12
CKIO to RDY# low
5424
18
ns
t13
CSn# high to RDY# high
5354
14
ns
t14
Falling edge CKIO to RDY# high impedance
5384
14
ns
t15
D[15:0] setup to 2nd CKIO after BS# (write cycle) (see note 1)
10
ns
t16
D[15:0] hold (write cycle)
00
ns
t17
RDY# falling edge to D[15:0] valid (read cycle)
02
ns
t18
Rising edge RD# to D[15:0] high impedance (read cycle)
5313
12
ns


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