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S1D13706 Datasheet(PDF) 30 Page - Epson Company

Part # S1D13706
Description  S1D13706 Embedded Memory LCD Controller
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Manufacturer  EPSON [Epson Company]
Direct Link  http://www.epsondevice.com
Logo EPSON - Epson Company

S1D13706 Datasheet(HTML) 30 Page - Epson Company

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Page 30
Epson Research and Development
Vancouver Design Center
S1D13706
Hardware Functional Specification
X31B-A-001-09
Issue Date: 2004/02/09
4.6 LCD Interface Pin Mapping
Note
1 GPIO pins must be configured as outputs (CNF3 = 0 at RESET#) when the HR-TFT or
D-TFD interface is selected.
2 These pin mappings use signal names commonly used for each panel type, however
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
Section 6.4, “Display Interface” on page 56.
3 When the HR-TFT interface is selected (REG[10h] bits 1-0 = 10), this GPO can be
used to control the HR-TFT MOD signal. Note this is not the same signal as the
S1D13706 DRDY(MOD) signal used for passive panels.
Table 4-9: LCD Interface Pin Mapping
Pin Name
Monochrome Passive
Panel
Color Passive Panel
Color TFT Panel
Single
Single
Others
Sharp HR-
TFT1
Epson
D-TFD1
4-bit
Format 1
8-bit
Format 2
8-bit
16-Bit
4-bit
8-bit
9-bit
12-bit
18-bit
18-bit
18-bit
FPFRAME
FPFRAME
SPS
DY
FPLINE
FPLINE
LP
LP
FPSHIFT
FPSHIFT
DCLK
XSCL
DRDY
MOD
FPSHIFT2
MOD
DRDY
no connect
GCP
FPDAT0
driven 0
D0
driven 0
D0 (B5)2
D0 (G3)2
D0 (R6)2
R2
R3
R5
R5
R5
FPDAT1
driven 0
D1
driven 0
D1 (R5)2
D1 (R3)2
D1 (G5)2
R1
R2
R4
R4
R4
FPDAT2
driven 0
D2
driven 0
D2 (G4)2
D2 (B2)2
D2 (B4)2
R0
R1
R3
R3
R3
FPDAT3
driven 0
D3
driven 0
D3 (B3)2
D3 (G2)2
D3 (R4)2
G2
G3
G5
G5
G5
FPDAT4
D0
D4
D0 (R2)2
D4 (R3)2
D4 (R2)2
D8 (B5)2
G1
G2
G4
G4
G4
FPDAT5
D1
D5
D1 (B1)2
D5 (G2)2
D5 (B1)2
D9 (R5)2
G0
G1
G3
G3
G3
FPDAT6
D2
D6
D2 (G1)2
D6 (B1)2
D6 (G1)2
D10 (G4)2
B2
B3
B5
B5
B5
FPDAT7
D3
D7
D3 (R1)2
D7 (R1)2
D7 (R1)2
D11 (B3)2
B1
B2
B4
B4
B4
FPDAT8
driven 0
driven 0
driven 0
driven 0
driven 0
D4 (G3)2
B0
B1
B3
B3
B3
FPDAT9
driven 0
driven 0
driven 0
driven 0
driven 0
D5 (B2)2
driven 0
R0
R2R2R2
FPDAT10
driven 0
driven 0
driven 0
driven 0
driven 0
D6 (R2)2
driven 0
driven 0
R1R1R1
FPDAT11
driven 0
driven 0
driven 0
driven 0
driven 0
D7 (G1)2
driven 0
driven 0
R0R0R0
FPDAT12
driven 0
driven 0
driven 0
driven 0
driven 0
D12 (R3)2
driven 0
G0
G2G2G2
FPDAT13
driven 0
driven 0
driven 0
driven 0
driven 0
D13 (G2)2
driven 0
driven 0
G1G1G1
FPDAT14
driven 0
driven 0
driven 0
driven 0
driven 0
D14 (B1)2
driven 0
driven 0
G0G0G0
FPDAT15
driven 0
driven 0
driven 0
driven 0
driven 0
D15 (R1)2
driven 0
B0
B2B2B2
FPDAT16
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
B1B1B1
FPDAT17
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
B0B0B0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
PS
XINH
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
CLS
YSCL
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
GPIO2
REV
FR
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
SPL
FRS
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
(output only)
RES
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
(output only)
DD_P1
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
(output only)
YSCLD
GPO
GPO (General Purpose Output)
MOD3
GPO
CVOUT
CVOUT
PWMOUT
PWMOUT


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