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S1D13706 Datasheet(PDF) 21 Page - Epson Company

Part # S1D13706
Description  S1D13706 Embedded Memory LCD Controller
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Manufacturer  EPSON [Epson Company]
Direct Link  http://www.epsondevice.com
Logo EPSON - Epson Company

S1D13706 Datasheet(HTML) 21 Page - Epson Company

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Epson Research and Development
Page 21
Vancouver Design Center
Hardware Functional Specification
S1D13706
Issue Date: 2004/02/09
X31B-A-001-09
4.3 Pin Descriptions
Key:
a LVTTL is Low Voltage TTL (see Section 5, “D.C. Characteristics” on page 31).
4.3.1 Host Interface
I
=
Input
O=
Output
IO
=
Bi-Directional (Input/Output)
P=
Power pin
LIS
=
LVTTLa Schmitt input
LI
=
LVTTL input
LB2A
=
LVTTL IO buffer (6mA/-6mA@3.3V)
LB3P
=
Low noise LVTTL IO buffer (12mA/-12mA@3.3V)
LO3
=
Low noise LVTTL Output buffer (12mA/-12mA@3.3V)
LB3M
=
Low noise LVTTL IO buffer with input mask (12mA/-12mA@3.3V)
T1
=
Test mode control input with pull-down resistor (typical value of 50
Ω at 3.3V)
Hi-Z
=
High Impedance
Table 4-2: Host Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
Voltage
RESET#
State
Description
AB0
I
5
LIS
HIOVDD
0
This input pin has multiple functions.
• For Generic #1, this pin is not used and should be connected
to VSS.
• For Generic #2, this pin inputs system address bit 0 (A0).
• For SH-3/SH-4, this pin is not used and should be connected
to VSS.
• For MC68K #1, this pin inputs the lower data strobe (LDS#).
• For MC68K #2, this pin inputs system address bit 0 (A0).
• For REDCAP2, this pin is not used and should be connected
to VSS.
• For DragonBall, this pin is not used and should be connected
to VSS.
See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
summary.
AB[16:1]
I
87-99,
2-4
LI
HIOVDD
0
System address bus bits 16-1.


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