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S1D13706 Datasheet(PDF) 90 Page - Epson Company

Part # S1D13706
Description  S1D13706 Embedded Memory LCD Controller
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Manufacturer  EPSON [Epson Company]
Direct Link  http://www.epsondevice.com
Logo EPSON - Epson Company

S1D13706 Datasheet(HTML) 90 Page - Epson Company

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Epson Research and Development
Vancouver Design Center
S1D13706
Hardware Functional Specification
X31B-A-001-09
Issue Date: 2004/02/09
7 Clocks
7.1 Clock Descriptions
7.1.1 BCLK
BCLK is an internal clock derived from CLKI. BCLK can be a divided version (
÷1, ÷2, ÷3,
÷4) of CLKI. CLKI is typically derived from the host CPU bus clock.
The source clock options for BCLK may be selected as in the following table.
Note
For synchronous bus interfaces, it is recommended that BCLK be set the same as the
CPU bus clock (not a divided version of CLKI) e.g. SH-3, SH-4.
Note
The CLKI
÷ 3 and CLKI ÷ 4 options may not work properly with bus interfaces with
short back-to-back cycle timing.
7.1.2 MCLK
MCLK provides the internal clock required to access the embedded SRAM. The S1D13706
is designed with efficient power saving control for clocks (clocks are turned off when not
used); reducing the frequency of MCLK does not necessarily save more power.
Furthermore, reducing the MCLK frequency relative to the BCLK frequency increases the
CPU cycle latency and so reduces screen update performance. For a balance of power
saving and performance, the MCLK should be configured to have a high enough frequency
setting to provide sufficient screen refresh as well as acceptable CPU cycle latency.
The source clock options for MCLK may be selected as in the following table.
Table 7-1: BCLK Clock Selection
Source Clock Options
BCLK Selection
CLKI
CNF[7:6] = 00
CLKI
÷2
CNF[7:6] = 01
CLKI
÷3
CNF[7:6] = 10
CLKI
÷4
CNF[7:6] = 11
Table 7-2: MCLK Clock Selection
Source Clock Options
MCLK Selection
BCLK
REG[04h] bit 5,4 = 00
BCLK
÷2
REG[04h] bit 5,4 = 01
BCLK
÷3
REG[04h] bit 5,4 = 10
BCLK
÷4
REG[04h] bit 5,4 = 11


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