PEEL18LV8ZTI-15 datasheet(8/10 Pages) ANACHIP

Part #	PEEL18LV8ZTI-15

Description	CMOS Programmable Electrically Erasable Logic Device

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Manufacturer	ANACHIP [Anachip Corp]

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8 / 10 page

Anachip Corp.

www.anachip.com.tw

Rev. 1.0 Dec 16, 2004

8/10

Table 4 - A.C. Electrical Characteristics

Over the operating range

9

-15/I-15

3V

±10% 3.3V±10%

Symbol

Parameter

Min Max Min Max

Units

tPD

Input

6 to non-registered output in continuous mode13

20

15

ns

tOE

Input

6 to output enable7

20

15

ns

tOD

Input

6 to output disable7

20

15

ns

tCO1

Clock to Output

17

12

ns

tCO2

Clock to comb output delay via internal registered

feedback

30

25

ns

tCF

Clock to Feedback

13

8

ns

tSC

Input

6 or feedback setup to clock

17

12

ns

tHC

Input

6 hold after clock

0

ns

tCL, tCH

Clock low time, clock high time

9

15

10

ns

tCP

Min clock period Ext (tSC + tCO1 )

32

24

ns

fMAX1

Internal feedback 1/ (tSC + tCF)

12

33.3

50

MHz

fMAX2

External Feedback (1/ tCP)

12

31.25

41.67

MHz

fMAX3

No Feedback 1/ (tCL + tCH)

12

33.3

50

MHz

tAW

Asynchronous Reset Pulse Width

20

15

ns

tAP

Input to Asynchronous Reset

20

15

ns

tAR

Asynchronous Reset recovery time

20

15

ns

tRESET

Power-on reset time for registers in clear state

14

5

µs

Inputs I/O,

Registered Feedback,

Synchronous Preset

Clock

Asynchronous

Reset

Registered

Outputs

Combinatorial

Outputs

Figure 7 - Switching Waveforms

Notes:

1.

Minimum DC input is -0.5V, however, inputs may undershoot to

-2.0V for periods less than 20 ns.

2.

VI and VO are not specified for program / verify operation.

3.

The Supply Voltage range of 2.7 to 3.6V was chosen to allow

this part to be used in both 3V

±10% and 3.3V ±10%

applications.

4.

Test Points for Clock and VCC in tR and tF are referenced at

the 10% and 90% levels.

5.

I/O pins are 0V and VCC .

6.

"Input" refers to an input pin signal.

7.

tOE is measured from input transition to V REF

± 0.1V, TOD is

measured from input transition to VOH -0.1V or VOL +0.1V;

VREF =VL.

8.

Capacitances are tested on a sample basis.

9.

Test conditions assume: signal transition times of 3ns or less

from the 10% and 90% points, timing reference levels of 1.5V

(Unless otherwise specified).

10.

Test one output at a time for duration of less than 1 second.

11.

ICC for a typical application: This parameter is tested with the

device programmed as an 8-bit Counter.

12.

Parameters are not 100% tested. Specifications are based on

initial characterization and are tested after any design process

modification that might affect operational frequency.

13.

tPD , tOE , tOD , tCO , tSC , and tAP are approximately 5 ns.

slower on the first transaction from sleep mode.

14.

All inputs at GND.

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