This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights

under any patent accompany the sale of the product.

Rev. 1.0 Dec 16, 2004

1/10

PEEL™ 18LV8Z-15 / I-15

CMOS Programmable Electrically Erasable Logic Device

Features

•

Low Voltage, Ultra Low Power Operation

- Vcc = 2.7 to 3.6 V

- Icc = 5 µA (typical) at standby

- Icc = 1.5 mA (typical) at 1 MHz

- Meets JEDEC LV Interface Spec (JEDSD8-A)

- 5 Volts tolerant inputs and I/O’s

•

CMOS Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

•

Application Versatility

- Replaces random logic

- Super set of standard PLDs

- Pin and JEDEC compatible with 16V8

- Ideal for battery powered systems

- Replaces expensive oscillators

•

Architectural Flexibility

- Enhanced architecture fits in more logic

- 113 product terms x 36 input AND array

- 10 inputs and 8 I/O pins

- 12 possible macrocell configurations

- Asynchronous clear, Synchronous preset

- Independent output enables

- Programmable clock; pin 1 or p-term

- Programmable clock polarity

- 20 Pin DIP/SOIC/TSSOP and PLCC

- Schmitt triggers on clock and data inputs

•

Schmitt Trigger Inputs

- Eliminates external Schmitt trigger devices

- Ideal for encoder designs

General Description

The PEEL18LV8Z is a Programmable Electrically Erasable

Logic (PEEL) SPLD (Simple Programmable Logic Device)

that operates over the supply voltage range of 2.7V-3.6V

and features ultra-low, automatic "zero" power-down

operation. The PEEL18LV8Z is logically and functionally

similar to Anachip's 5V PEEL18CV8 and PEEL18CV8Z.

The "zero power" (25

µA max. Icc) power-down mode

makes the PEEL18LV8Z ideal for a broad range of battery-

powered portable equipment applications, from hand-held

meters

to

PCMCIA

modems.

EE-reprogrammability

provides both the convenience of fast reprogramming for

product development and quick product personalization in

manufacturing, including Engineering Change Orders.

The

differences

between

the

PEEL18LV8Z

and

PEEL18CV8 include the addition of programmable clock

polarity, p-term clock, and Schmitt trigger input buffers on

all inputs, including the clock. Schmitt trigger inputs allow

direct input of slow or noisy signals.

Like the PEEL18CV8, the PEEL18LV8Z is a logical

superset of the industry standard PAL16V8 SPLD. The

PEEL18LV8Z provides additional architectural features that

allow more logic to be incorporated into the design.

Anachip's JEDEC file translator allows easy conversion of

existing 20 pin PLD designs to the PEEL18LV8Z

architecture

without

the

need

for

redesign.

The

PEEL18LV8Z architecture allows it to replace over twenty

standard 20-pin DIP, SOIC, TSSOP and PLCC packages.

DIP

I/CLK1

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

GND

10

11

I

12

I/O

V

CC

20

I/O

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

1

I/CLK1

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

GND

20

V

CC

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I/O

TSSOP

12

I/O

11

I

1

I/CLK1

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

GND

20

V

CC

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I/O

SOIC

12

I/O

11

I

4

I

5

I

6

I

7

I

8

I

9 10 11 12 13

3

2

1

19

PLCC-J

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

20

Figure 1 - Pin Configuration

CLK MUX (Optional)

ª

Figure 2 - Block Diagram