Electronic Components Datasheet Search
  English  ▼

Delete All


Preview PDF Download HTML

PEEL18LV8Z Datasheet(PDF) 4 Page - Anachip Corp

Part No. PEEL18LV8Z
Description  CMOS Programmable Electrically Erasable Logic Device
Download  10 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ANACHIP [Anachip Corp]
Direct Link  
Logo ANACHIP - Anachip Corp

PEEL18LV8Z Datasheet(HTML) 4 Page - Anachip Corp

  PEEL18LV8Z Datasheet HTML 1Page - Anachip Corp PEEL18LV8Z Datasheet HTML 2Page - Anachip Corp PEEL18LV8Z Datasheet HTML 3Page - Anachip Corp PEEL18LV8Z Datasheet HTML 4Page - Anachip Corp PEEL18LV8Z Datasheet HTML 5Page - Anachip Corp PEEL18LV8Z Datasheet HTML 6Page - Anachip Corp PEEL18LV8Z Datasheet HTML 7Page - Anachip Corp PEEL18LV8Z Datasheet HTML 8Page - Anachip Corp PEEL18LV8Z Datasheet HTML 9Page - Anachip Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 10 page
background image
Anachip Corp.
Rev. 1.0 Dec 16, 2004
the asynchronous clear sets Q LOW, regardless of the
clock state. If both terms are satisfied simultaneously, the
clear will override the preset.
Output Polarity
Each macrocell can be configured to implement active-high
or active-low logic. Programmable polarity eliminates the
need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or
disabled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is switched into the high-impedance state.
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bi-
directional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Input/Feedback Select
The PEEL18LV8Z macrocell also provides control over the
feedback path. The input/feedback signal associated with
each I/O macrocell can be obtained from three different
locations; from the I/O input pin, from the Q output of the
flip-flop (registered feedback), or directly from the OR gate
(combinatorial feedback).
Bi-directional I/O
The input/feedback signal is taken from the I/O pin when
using the pin as a dedicated input or as a bi-directional I/O.
(Note that it is possible to create a registered output
function with a bi-directional I/O, refer to Figure 4).
Figure 4 - PEEL18LV8Z I/O Macro cell
Combinatorial Feedback
The signal-select multiplexer gives the macrocell the ability
to feedback the output of the OR gate, bypassing the
output buffer, regardless of whether the output function is
registered or combinatorial. This feature allows the creation
of asynchronous latches, even when the output must be
disabled. (Refer to configurations 5, 6, 7, and 8 in Figure 5.)
Registered Feedback
Feedback also can be taken from the register, regardless
of whether the output function is programmed to be
combinatorial or registered. When implementing a
combinatorial output function, registered feedback allows
for the internal latching of states without giving up the use
of the external output.
Programmable Clock Options
A unique feature of the PEEL18LV8Z is a programmable
clock multiplexer that allows the user to select true or
complement forms of either input pin or product-term clock
Operates in both 3 Volt and 3.3 Volt Systems
The PEEL18LV8Z is designed to operate with a V CC range
of 2.7 to 3.6 Volts D.C. This allows operation in both 3 Volt
10% (battery operated) and 3.3 Volt 10% (power supply
operated) systems. The propagation delay t PD is 5 ns
slower at the lower voltage, but this is typically not an issue
in battery-operated systems (see - A.C. Electrical
CharacteristicsTable 1 - Absolute Maximum Ratings- A.C.
Electrical Characteristics).
Schmitt Trigger Inputs
The PEEL18LV8Z has Schmitt trigger input buffers on all
inputs, including the clock. Schmitt trigger inputs allow
direct input of slow signals such as biomedical and sine
waves or clocks. They are also useful in cleaning up noisy
signals. This makes the PEEL18LV8Z especially desirable
in portable applications where the environment is less
Zero Power Feature
The CMOS PEEL18LV8Z features "Zero-Power" standby
operation for ultra-low power consumption. With the "Zero-
Power" feature, transition-detection circuitry monitors the
inputs, I/Os (including CLK) and feedbacks. If these signals
do not change for a period of time greater than
approximately three t PD 's, the outputs are latched in their
current state and the device automatically powers down.
When the next signal transition is detected, the device will
"wake up" for active operation until the signals stop

Html Pages

1  2  3  4  5  6  7  8  9  10 

Datasheet Download

Go To PDF Page

Link URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com

Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn