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AWR1243 Datasheet(PDF) 24 Page - Texas Instruments |
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AWR1243 Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 49 page  24 AWR1243 SWRS188 – MAY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: AWR1243 Specifications Copyright © 2017, Texas Instruments Incorporated (1) With an additional load capacitance CCM of 0 to 60 pF on the termination center tap at RX side of the lane (2) While driving CLOAD. Load capacitance includes 50 pF of transmission line capacitance, and 10 pF each for TX and RX. (3) When the output voltage is from 15% to 85% of the fully settled LP signal levels (4) Measured as average across any 50 mV segment of the output signal transition 5.9.5 Camera Serial Interface (CSI) The CSI is a MIPI D-PHY compliant interface for connecting this device to a camera receiver module. This interface is made of four differential lanes; each lane is configurable for carrying data or clock. The polarity of each wire of a lane is also configurable. Table 5-11, Figure 5-6, Figure 5-7, and Figure 5-8 describe the clock and data timing of the CSI. Table 5-11. CSI Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT HPTX HSTXDBR Data bit rate (1 or 2 data lane PHY) 150 900 Mbps (4 data lane PHY) 150 600 fCLK DDR clock frequency (1 or 2 data lane PHY) 75 450 MHz (4 data lane PHY) 75 300 ΔVCMTX(LF) Common-level variation from 75 to 450 MHz of CSI2 clock frequency –50 50 mVpeak tR and tF 20% to 80% rise time and fall time 150 ns 0.3 UI LPTX DRIVER tRLP and tFLP 15% to 85% rise time and fall time 25 ns tEOT (1) Time from start of THS-TRAIL period to start of LP-11 state 105 + 12*UI ns δV/δtSR (2) (3) (4) Slew rate. CLOAD = 0 to 5 pF 500 mV/ns Slew rate. CLOAD = 5 to 20 pF 200 Slew rate. CLOAD = 20 to 70 pF 100 CLOAD (2) Load capacitance 0 70 pF DATA-CLOCK Timing Specification UINOM Nominal unit interval (1, 2, or 3 data lane PHY) 1.11 13.33 ns Nominal unit interval (4 data lane PHY) 1.67 13.33 UIINST,MIN Minimum instantaneous Unit Interval (1, 2, or 3 data lane PHY) 1.033 0.975*U INOM – 0.05 ns Minimum instantaneous Unit Interval (4 data lane PHY) 1.131 TSKEW[TX] Data to clock skew measured at transmitter –0.15 0.15 UIINST, MIN CSI2 TIMING SPECIFICATION TCLK-MISS Time-out for receiver to detect absence of clock transitions and disable the clock lane HS-RX. 60 ns TCLK-POST Time that the transmitter continues to send HS clock after the last associated data lane has transitioned to lp mode. Interval is defined as the period from the end of THS-TRAIL to the beginning of TCLK-TRAIL. 60 ns + 52*UI ns TCLK-PRE Time that the HS clock shall be driven by the transmitter before any associated data lane beginning the transition from LP to HS mode. 8 ns TCLK-PREPARE Time that the transmitter drives the clock lane LP-00 line state immediately before the HS-0 line state starting the HS transmission. 38 95 ns TCLK-SETTLE Time interval during which the HS receiver should ignore any clock lane HS transitions, starting from the beginning of TCLK- PREPARE. 95 300 ns |
Similar Part No. - AWR1243_18 |
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Similar Description - AWR1243_18 |
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