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Clock Generator for Intel Grantsdale Chipset
CY28410
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07593 Rev. *C
Revised Sept. 28, 2204
Features
• Compliant with Intel CK410
• Supports Intel P4 and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100-MHz differential SRC clocks
• 96-MHz differential dot clock
• 48-MHz USB clocks
• 33-MHz PCI clock
• Low-voltage frequency select input
•I2C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
CPU
SRC
PCI
REF
DOT96
USB_48
x2 / x3
x6 / x7
x 9
x 1
x 1
x 1
Block Diagram
Pin Configuration
VDD_PCI
VSS_PCI
PCI4
PCI5
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
PCIF1
PCIF2
VDD_48
USB_48
VSS_48
DOT96T
DOT96C
FS_B/TEST_MODE
VTT_PWRGD#/PD
FS_A
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
PCI2
PCI1
SRCC5
CPUT2_ITP/SRCT7
VSSA
VDDA
IREF
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS_CPU
SDATA
SCLK
VDD_REF
XIN
VSS_REF
FS_C/TEST_SEL
REF
PCI0
CPUC2_ITP/SRCC7
SRC4-SATAT
SRC4_SATAC
VDD_SRC
VDD_SRC
SRCT6
SRCT5
VSS_SRC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
31
30
29
VDD_REF
XTAL
PLL Ref Freq
XOUT
XIN
OSC
SCLK
PLL1
I2C
Logic
VDD_48 MHz
SDATA
VDD_PCI
Divider
Network
VDD_CPU
FS_[C:A]
REF
VTT_PWRGD#
IREF
PCI[0:5]
PLL2
CPUT[0:1], CPUC[0:1],
VDD_SRC
SRCT[1:6], SRCC[1:6]
USB_48
PCI3
SRCC6
XOUT
56 SSOP/TSSOP
DOT96T
DOT96C
VDD_PCIF
PCIF[0:2]
CPU(T/C)2_ITP]
PD
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