AD5124 datasheet(23/36 Pages) AD

Part #	AD5124

Description	Quad Channel, 128-/256-Position, I2C/SPI, Nonvolatile Digital Potentiometer

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Manufacturer	AD [Analog Devices]

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23 / 36 page

Data Sheet

AD5124/AD5144/AD5144A

Rev. B | Page 23 of 36

THEORY OF OPERATION

The AD5124/AD5144/AD5144A digital programmable

potentiometers are designed to operate as true variable resistors

for analog signals within the terminal voltage range of VSS < VTERM <

VDD. The resistor wiper position is determined by the RDAC

register contents. The RDAC register acts as a scratchpad register

that allows unlimited changes of resistance settings. A secondary

register (the input register) can be used to preload the RDAC

register data.

The RDAC register can be programmed with any position setting

using the I2C or SPI interface (depending on the model). When

a desirable wiper position is found, this value can be stored in

the EEPROM memory. Thereafter, the wiper position is always

restored to that position for subsequent power-ups. The storing

of the EEPROM data takes approximately 15 ms; during this

time, the device is locked and does not acknowledge any new

command, preventing any changes from taking place.

RDAC REGISTER AND EEPROM

The RDAC register directly controls the position of the digital

potentiometer wiper. For example, when the RDAC register is

loaded with 0x80 (AD5144/AD5144A, 256 taps), the wiper is

connected to half scale of the variable resistor. The RDAC register

is a standard logic register; there is no restriction on the number

of changes allowed.

It is possible to both write to and read from the RDAC register

using the digital interface (see Table 14).

The contents of the RDAC register can be stored to the EEPROM

using Command 9 (see Table 14). Thereafter, the RDAC register

always sets at that position for any future on-off-on power

supply sequence. It is possible to read back data saved into the

EEPROM with Command 3 (see Table 14).

Alternatively, the EEPROM can be written to independently

using Command 11 (see Table 20).

INPUT SHIFT REGISTER

For the AD5124/AD5144/AD5144A, the input shift register is

16 bits wide, as shown in Figure 4. The 16-bit word consists of

four control bits, followed by four address bits and by eight

data bits.

If the AD5124 RDAC or EEPROM registers are read from or

written to, the lowest data bit (Bit 0) is ignored.

Data is loaded MSB first (Bit 15). The four control bits determine

the function of the software command, as listed in Table 14 and

Table 20.

SERIAL DATA DIGITAL INTERFACE SELECTION, DIS

The AD5124/AD5144 LFSCP provides the flexibility of a selectable

interface. When the digital interface select (DIS) pin is tied low,

the SPI mode is engaged. When the DIS pin is tied high, the I2C

mode is engaged.

SPI SERIAL DATA INTERFACE

The AD5124/AD5144 contain a 4-wire, SPI-compatible digital

interface (SDI, SYNC, SDO, and SCLK). The write sequence

begins by bringing the SYNC line low. The SYNC pin must be

held low until the complete data-word is loaded from the SDI

pin. Data is loaded in at the SCLK falling edge transition, as

shown in Figure 6. When SYNC returns high, the serial data-

word is decoded according to the instructions in Table 20.

To minimize power consumption in the digital input buffers

when the part is enabled, operate all serial interface pins close

to the VLOGIC supply rails.

SYNC Interruption

In a standalone write sequence for the AD5124/AD5144,

the SYNC line is kept low for 16 falling edges of SCLK, and the

instruction is decoded when SYNC is pulled high. However, if

the SYNC line is kept low for less than 16 falling edges of SCLK,

the input shift register content is ignored, and the write sequence is

considered invalid.

SDO Pin

The serial data output pin (SDO) serves two purposes: to read back

the contents of the control, EEPROM, RDAC, and input registers

using Command 3 (see Table 14 and Table 20), and to connect the

AD5124/AD5144 in daisy-chain mode.

The SDO pin contains an internal open-drain output that needs an

external pull-up resistor. The SDO pin is enabled when SYNC is

pulled low, and the data is clocked out of SDO on the rising

edge of SCLK, as shown in Figure 6 and Figure 7.

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