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AD5122 Datasheet(PDF) 13 Page - Analog Devices

Part No. AD5122
Description  Dual Channel, 128-/256-Position, SPI, Nonvolatile Digital Potentiometer
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5122 Datasheet(HTML) 13 Page - Analog Devices

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Data Sheet
AD5122/AD5142
Rev. C | Page 13 of 32
1
2
3
4
5
6
7
8
INDEP
A1
W1
B1
RESET
A2
VSS
GND
16
15
14
13
12
11
10
9
SDO
SDI
SCLK
VLOGIC
VDD
W2
B2
AD5122/
AD5142
TOP VIEW
(Not to Scale)
SYNC
Figure 7. 16-Lead TSSOP, SPI Interface Pin Configuration
Table 9. 16-Lead TSSOP, SPI Interface Pin Function Descriptions
Pin No.
Mnemonic
Description
1
INDEP
Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from the associated
memory location. If INDEP is enabled, it cannot be disabled by software.
2
RESET
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is
not used, tie RESET to VLOGIC.
3
GND
Ground Pin, Logic Ground Reference.
4
A1
Terminal A of RDAC1. V
SS ≤ VA ≤ VDD.
5
W1
Wiper Terminal of RDAC1. V
SS ≤ VW ≤ VDD.
6
B1
Terminal B of RDAC1. V
SS ≤ VB ≤ VDD.
7
V
SS
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
8
A2
Terminal A of RDAC2. V
SS ≤ VA ≤ VDD.
9
W2
Wiper Terminal of RDAC2. V
SS ≤ VW ≤ VDD.
10
B2
Terminal B of RDAC2. V
SS ≤ VB ≤ VDD.
11
V
DD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
12
V
LOGIC
Logic Power Supply; 1.8 V to V
DD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
13
SCLK
Serial Clock Line. Data is clocked in at the logic low transition.
14
SDI
Serial Data Input.
15
SDO
Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor.
16
SYNC
Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register.


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