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AD5122 Datasheet(PDF) 12 Page - Analog Devices

Part No. AD5122
Description  Dual Channel, 128-/256-Position, SPI, Nonvolatile Digital Potentiometer
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5122 Datasheet(HTML) 12 Page - Analog Devices

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AD5122/AD5142
Data Sheet
Rev. C | Page 12 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
GND
A1
W1
B1
SCLK
SDI
VLOGIC
VDD
12
11
10
1
3
4
9
2
PIN 1
INDICATOR
NOTES
1.EXPOSED PAD. CONNECT THE EXPOSED PAD TO THE
POTENTIAL OF THE VSS PIN, OR, ALTERNATIVELY, LEAVE
IT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED
THAT THE PAD BE THERMALLY CONNECTED TO A COPPER
PLANE FOR ENHANCED THERMAL PERFORMANCE.
AD5122/
AD5142
TOP VIEW
(Not to Scale)
Figure 6. 16-Lead LFCSP Pin Configuration
Table 8. 16-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
GND
Ground Pin, Logic Ground Reference.
2
A1
Terminal A of RDAC1. V
SS ≤ VA ≤ VDD.
3
W1
Wiper Terminal of RDAC1. V
SS ≤ VW ≤ VDD.
4
B1
Terminal B of RDAC1. V
SS ≤ VB ≤ VDD.
5
V
SS
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
6
A2
Terminal A of RDAC2. V
SS ≤ VA ≤ VDD.
7
W2
Wiper Terminal of RDAC2. V
SS ≤ VW ≤ VDD.
8
B2
Terminal B of RDAC2. V
SS ≤ VB ≤ VDD.
9
V
DD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
10
V
LOGIC
Logic Power Supply; 1.8 V to V
DD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
11
SCLK
Serial Clock Line. Data is clocked in at the logic low transition.
12
SDI
Serial Data Input.
13
SDO
Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor.
14
SYNC
Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register.
15
INDEP
Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from the associated
memory location. If INDEP is enabled, it cannot be disabled by software.
16
RESET
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is
not used, tie RESET to VLOGIC.
EPAD
Exposed Pad. Connect this exposed pad to the potential of the V
SS pin, or, alternatively, leave it electrically
unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced
thermal performance.


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