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AD5122 Datasheet(PDF) 9 Page - Analog Devices

Part No. AD5122
Description  Dual Channel, 128-/256-Position, SPI, Nonvolatile Digital Potentiometer
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5122 Datasheet(HTML) 9 Page - Analog Devices

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Data Sheet
AD5122/AD5142
Rev. C | Page 9 of 32
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface1
Parameter2
Test Conditions/Comments
Min
Typ
Max
Unit
Description
t
1
V
LOGIC > 1.8 V
20
ns
SCLK cycle time
V
LOGIC = 1.8 V
30
ns
t
2
V
LOGIC > 1.8 V
10
ns
SCLK high time
V
LOGIC = 1.8 V
15
ns
t
3
V
LOGIC > 1.8 V
10
ns
SCLK low time
V
LOGIC = 1.8 V
15
ns
t
4
10
ns
SYNC to SCLK falling edge setup time
t
5
5
ns
Data setup time
t
6
5
ns
Data hold time
t
7
10
ns
SYNC rising edge to next SCLK fall ignored
t
8
3
20
ns
Minimum SYNC high time
t
9
4
50
ns
SCLK rising edge to SDO valid
t
10
500
ns
SYNC rising edge to SDO pin disable
1 Refer to the AN-1248 for additional information about the serial peripheral interface.
2 All input signals are specified with t
r = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 Refer to t
EEPROM_PROGRAM and tEEPROM_READBACK for memory commands operations (see Table 5).
4 R
PULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF.
Table 5. Control Pins
Parameter
Min
Typ
Max
Unit
Description
t
1
0.1
10
µs
RESET low time
t
EEPROM_PROGRAM
1
15
50
ms
Memory program time (not shown in Figure 5)
t
EEPROM_READBACK
7
30
µs
Memory readback time (not shown in Figure 5)
t
POWER_UP
2
75
µs
Start-up time (not shown in Figure 5)
t
RESET
30
µs
Reset EEPROM restore time (not shown in Figure 5)
1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
2 Maximum time after V
DD − VSS is equal to 2.3 V.


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