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AD5122 Datasheet(PDF) 5 Page - Analog Devices

Part No. AD5122
Description  Dual Channel, 128-/256-Position, SPI, Nonvolatile Digital Potentiometer
Download  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5122 Datasheet(HTML) 5 Page - Analog Devices

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Data Sheet
AD5122/AD5142
Rev. C | Page 5 of 32
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS9
Bandwidth
BW
−3 dB
R
AB = 10 kΩ
3
MHz
R
AB = 100 kΩ
0.43
MHz
Total Harmonic Distortion
THD
V
DD/VSS = ±2.5 V, VA = 1 V rms,
V
B = 0 V, f = 1 kHz
R
AB = 10 kΩ
−80
dB
R
AB = 100 kΩ
−90
dB
Resistor Noise Density
e
N_WB
Code = half scale, T
A = 25°C,
f = 10 kHz
R
AB = 10 kΩ
7
nV/√Hz
R
AB = 100 kΩ
20
nV/√Hz
V
W Settling Time
t
S
V
A = 5 V, VB = 0 V, from
zero scale to full scale,
±0.5 LSB error band
R
AB = 10 kΩ
2
µs
R
AB = 100 kΩ
12
µs
Crosstalk (C
W1/CW2)
C
T
R
AB = 10 kΩ
10
nV-sec
R
AB = 100 kΩ
25
nV-sec
Analog Crosstalk
C
TA
−90
dB
Endurance10
T
A = 25°C
1
Mcycles
100
kcycles
Data Retention11, 12
50
Years
1 Typical values represent average readings at 25°C, V
DD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at V
WB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 P
DISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use V
DD/VSS = ±2.5 V, and VLOGIC = 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
12 50 years applies to an endurance of 1k cycles. An endurance of 100k cycles has an equivalent retention lifetime of 5 years.


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