Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

CS1089 Datasheet(PDF) 5 Page - ON Semiconductor

Part No. CS1089
Description  Vacuum Fluorescent Display Tube Driver
Download  12 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo 

CS1089 Datasheet(HTML) 5 Page - ON Semiconductor

 
Zoom Inzoom in Zoom Outzoom out
 5 / 12 page
background image
CS1089
http://onsemi.com
5
AN1 – AN23: 2.0 mA
VREG
POR
GRID1
GRID2 GRID3
AN1
AN2
AN3
AN23
AN24
AN25
AN26
AN27
AN28
AN29
VBB
GND
GREN
STB
DIN
CLK
DOUT
METAL MASK ROM
Output Drive Capability
Grid Outputs: 5 mA
AN24 – AN29: 20 mA
DQ
LE
DQ
CLK
R
VREG
VREG
VREG
VREG
VREG
VREG
Figure 2. Block Diagram
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
OPERATION DESCRIPTION
Upon the initial application of power, the power on reset
function will cause all of the anode and grid driver outputs
to be off and all shift register outputs to be set low. Data is
fed into the shift register through the DIN pin at the rising
edge of the CLK input. Thirty two bits of data are capable of
being stored by the shift register. Once the desired pattern is
stored in the shift register, it can be transferred to the latch
by setting the STB input high. The output of each latch
drives its corresponding output stage. A logic high input to
the shift register/latch will cause the corresponding output
to turn on. A logic low input to the shift register/latch will
cause the corresponding output to turn off. Please note that
if the STB is held high, the outputs of the latch reflect the
outputs of the corresponding shift register bits and will
change if data is shifted in.
The three GRID outputs are gated by the GREN input.
When GREN is low, the GRID outputs are forced low
regardless of the state of the corresponding latch output.
When GREN is high, the GRID outputs correspond to the
state of their respective latch outputs. The anode outputs,
AN1 to AN29 are always enabled.
The DOUT pin is the output of the last stage of the shift
register to allow serial cascading of this IC with other
devices. Data from the last stage of the shift register is
supplied to the DOUT pin delayed by 1/2 CLK cycle. Data on
the DOUT output changes with the falling edges of the CLK
to prevent logic race conditions between the CLK and the
DIN of the next IC in the serial chain.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn