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AM29SL400CB110EI Datasheet(PDF) 18 Page - SPANSION |
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AM29SL400CB110EI Datasheet(HTML) 18 Page - SPANSION |
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18 / 44 page  16 March 3, 2005 Ad vance Inform ati o n Note: See Table 5 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not re- quire the system to preprogram prior to erase. The Embedded Erase algorithm automatically prepro- grams and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings dur- ing these operations. Table 5 on page 18 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Em- bedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation im- mediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status‚ on page 18 for information on these status bits. When the Embed- ded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 4‚ on page 17 illustrates the algorithm for the erase operation. See Erase/Program Operations‚ on page 30 for parameters, and to Figure 18 for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sec- tor erase command. Table 5 on page 18 shows the address and data requirements for the sector erase command sequence. The device does not require the system to prepro- gram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electri- cal erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the num- ber of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and com- mand might not be accepted, and erasure may be- gin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time be- tween additional sector erase commands can be as- sumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out pe- riod resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sec- tor erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- mands are ignored. Note that a hardware reset during the sector erase operation immediately termi- nates the operation. The Sector Erase command se- quence should be reinitiated once the device has returned to reading array data, to ensure data integ- rity. START Write Program Command Sequence Data Poll from System Verify Data? No Yes Last Address? No Yes Programming Completed Increment Address Embedded Program algorithm in progress |
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