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74LVC1G14 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74LVC1G14
Description  Single Schmitt-trigger inverter
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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 2 page
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2004 Sep 10
2
Philips Semiconductors
Product specification
Single Schmitt-trigger inverter
74LVC1G14
FEATURES
• Wide supply voltage range from 1.65 V to 5.5 V
• High noise immunity
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
•±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Unlimited rise and fall times
• Input accepts voltages up to 5 V
• Multiple package options
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 °C to +85 °C and
−40 °C to +125 °C.
DESCRIPTION
The 74LVC1G14 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The input can be driven from either 3.3 V or 5 V devices.
This feature allows the use of this device in a mixed
3.3 V and 5 V environment.
Schmitt-trigger action at the input makes the circuit
tolerant for slower input rise and fall time.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G14 provides the inverting buffer function with
Schmitt-trigger action.
QUICK REFERENCE DATA
Ground = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay A to Y
VCC = 1.8 V; CL = 30 pF; RL =1kΩ
4.1
ns
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
2.8
ns
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
3.0
ns
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω
2.2
ns
CI
input capacitance
5
pF
CPD
power dissipation capacitance per buffer
notes 1 and 2
15.4
pF




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